Abstract: A layout of flash memory having symmetric select transistors includes a memory cell array and a polysilicon gate. The polysilicon gate forms a plurality of select transistors in coordination with a plurality of pairs of sources/drains, so as to connect to the memory cell array. The polysilicon is perpendicularly extended toward a direction of the memory cell array, thereby overcoming a drawback as select transistors being unsymmetrical in a prior flash memory structure.

Abstract: Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 ? to 600 ?, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.

Abstract: The present invention relates to a circuit assembly with at least two semiconductor components, each having terminals, whereby at least one terminal of the first semiconductor component is connected to a terminal of the other semiconductor component in an electrically conductive manner. The circuit assembly damps high-frequency oscillations that occur during switching operations. An eddy-current damping structure is provided above said assembly at a distance from the semiconductor components or said semiconductor components are directly connected to each other by means of a high-resistance wire connection in addition to the existent electroconductive connection.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A digital power supply system provides a supply voltage to semiconductor circuits. The power supply system utilizes a pulse width modulator to output a signal into a LC filter that generates a DC supply voltage. The width of the pulses output by the pulse width modulator are defined by an encoder that generates width information in response to a propagation delay detector that measures the propagation delay of a first clock signal when clocked by a second clock signal.

Abstract: Methods for forming an oxynitride dielectric in a semiconductor device are disclosed. In the method, an oxynitride layer is grown on a semiconductor device. The oxynitride layer is then annealed at a temperature of about 400° C. for about 20 minutes. Further, the annealing may be performed in a nitrogen ambient or a nitrogen ambient including an oxygen concentration of less than about 1 to about 10 parts per billion.

Abstract: A chip-type light-emitting semiconductor device includes: a substrate 4; a blue LED 1 mounted on the substrate 4; and a luminescent layer 3 made of a mixture of yellow/yellowish phosphor particles 2 and a base material 13 (translucent resin). The yellow/yellowish phosphor particles 2 is a silicate phosphor which absorbs blue light emitted by the blue LED 1 to emit a fluorescence having a main emission peak in the wavelength range from 550 nm to 600 nm, inclusive, and which contains, as a main component, a compound expressed by the chemical formula: (Sr1?a1?b1?xBaa1Cab1Eux)2SiO4 (0?a1?0.3, 0?b1?0.8 and 0<x<1). The silicate phosphor particles disperse substantially evenly in the resin easily. As a result, excellent white light is obtained.

Abstract: A semiconductor light emitting device is formed by adhering a semiconductor layered portion having a light emitting layer forming portion to a conductive substrate via a metal layer. The metal layer has at least a first metal layer for ohmic contact with the semiconductor layered portion, a second metal layer made of Ag, and a third metal layer made of a metal which allows adhesion to the conductive substrate at a low temperature. As a result, the rate of reflection of light from the metal layer increases due to the presence of Ag in the metal layer. Further, the metal in the metal layer is prohibited from diffusing into the semiconductor layer, so that the semiconductor layer does not absorb light. And therefore the brightness of the semiconductor light emitting device can further be increased.

Abstract: A phase-changeable memory device comprises a substrate and an access transistor formed in and/or on the substrate. Laterally spaced apart first and second conductive patterns are disposed on the substrate and have opposing sidewalls. A conductor electrically connects the first conductive region to a source/drain region of the access transistor. A phase-changeable material region is disposed between the first and second conductive patterns and contacts the opposing sidewalls of the first and second conductive patterns. Contact areas between the conductive patterns and the phase-changeable material region are preferably substantially smaller than contact areas at which the conductive patterns contact conductors (e.g., vias) connected thereto, such that high current densities may be developed in the phase-changeable material. Methods of fabricating such devices are also discussed.

Abstract: Fluidic self-assembly may be utilized to form a stack of two integrated circuits. The integrated circuits may include surface mount electrical connections and surface features that control the alignment between the integrated circuits. In particular, the contacts may be provided on one side of each integrated circuit and surface features may cause the integrated circuits to align with one another in an immersion fluid. The aligned circuits may join to form physical and electrical connections. The resulting structure may be a stack of two integrated circuits electrically coupled to one another.

Abstract: A process for fabricating thin film transistors is disclosed, which comprises a two-step laser annealing process as follows: crystallizing the channel portion by irradiating the channel portion with an irradiation beam; and modifying the electric properties of the source and the drain by irradiating the source and the drain with an irradiation beam in a step independent to the first step of crystallizing the channel portion.

Abstract: Disclosed is a semiconductor device comprises a substrate, a wiring formed into a predetermined pattern above the substrate and provided with a pad portion for external connection, an interlayer insulating film formed above the substrate to cover the wiring and provided with a contact hole for a contact to a pad portion of the wiring, and a cap layer formed on the interlayer insulating film and electrically connected, via the contact hole formed in the interlayer insulating film, with the pad portion of the wiring, wherein one end portion of the cap layer is positioned at the contact hole and the cap layer is extended from the contact hole in a direction which is different from that of the pattern of the wiring.

Abstract: An integrated circuit is disclosed herein. One embodiment of the integrated circuit comprises a power supply conductor, a circuit, at least one bypass capacitor, and an electrostatic protection circuit. The circuit may be located on a first piece of silicon, which may be located on a first insulator. The bypass capacitor may be located on a second piece of silicon, which may be located on second insulator. The electrostatic protection circuit may be located on a third piece of silicon, which may be located on a third insulator. The electrostatic protection circuit is connected to the power supply conductor by way of a first line. The bypass capacitor and the circuit are connected to the power supply conductor by way of a second line. The resistance of the second line is greater than the resistance of the first line.

Abstract: A current-in-plane magnetic sensor comprises a sensor stack including first and second layers of ferromagnetic material, a first nano-oxide layer positioned adjacent to the first layer of ferromagnetic material, and a layer of non-magnetic material positioned between the first and second layers of ferromagnetic material, wherein the thickness of the non-magnetic layer is selected to provide antiferromagnetic coupling between the first and second ferromagnetic layers, a magnetic field source for biasing the directions of magnetization of the first and second layers of ferromagnetic material in directions approximately 90° with respect to each other, a first lead connected to a first end of the sensor stack, and a second lead connected to a second end of the sensor stack. Disc drives that use the current-in-plane magnetic sensor are also included.

Abstract: A method and apparatus that produces highly ordered, nanosized particle arrays on various substrates. These regular arrays may be used as masks to deposit and grow other nanoscale materials.

Abstract: Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the microelectronic workpiece further includes a plurality of dies formed on the device side of the substrate, a dielectric layer over the dies, and a plurality of bond-pads on the dielectric layer. The dies have integrated circuitry and a plurality of bond-pads electrically coupled to the integrated circuitry. The ball-pads are arranged in ball-pad arrays over corresponding dies on the substrate. The ball-pads of one array, for example, are electrically coupled to the bond-pads of the corresponding die. The microelectronic workpiece of this embodiment further includes a protective film over the dielectric layer.

Abstract: A structure is constructed having a through hole in a substrate of silicon or the like by a decreased number of steps in production and with improved reliability. A silicon nitride film is formed in contact with an upper surface of a silicon oxide film at least on a portion of the substrate near the edge of a through hole, thereby improving step coverage of the silicon nitride film. The silicon oxide film and silicon nitride film function as a membrane during formation of the through hole by etching from the back side of the substrate.

Abstract: A soft transparent adhesive layer is utilized to bond a transparent substrate material onto an AlGaInP light-emitting diode epitaxy on a GaAs substrate, and the GaAs substrate is next removed entirely. Then, a mesa etching process is performed to form a first top surface and a second top surface on the AlGaInP light-emitting diode epitaxy for respectively exposing an n-type layer and a p-type layer in the AlGaInP light-emitting diode epitaxy. Next, a metal reflective layer and a barrier layer are formed on the AlGaInP light-emitting diode epitaxy in turn, and electrodes are finally fabricated on the barrier layer.

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate a type of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.