Abstract: A nitride semiconductor laser device using a group III nitride semiconductor also as a substrate offers excellent operation characteristics and a long laser oscillation life. In a layered structure of a group III nitride semiconductor formed on a GaN substrate, a laser optical waveguide region is formed elsewhere than right above a dislocation-concentrated region extending so as to vertically penetrate the substrate, and electrodes are formed on the top surface of the layered structure and on the bottom surface of the substrate elsewhere than right above or below the dislocation-concentrated region. In a portion of the top surface of the layered structure and in a portion of the bottom surface of the substrate right above and below the dislocation-concentrated region, dielectric layers may be formed to prevent the electrodes from making contact with those regions.

Abstract: A method of making a semiconductor chip assembly includes mechanically attaching a semiconductor chip that includes a conductive pad to a routing line, mechanically attaching and electrically connecting a metal particle to the routing line, wherein the routing line extends laterally beyond the metal particle towards the chip and the chip and the metal particle extend vertically beyond the routing line in the same direction, forming an encapsulant after attaching the chip and the metal particle to the routing line wherein the chip and the metal particle are embedded in the encapsulant, and forming a connection joint that electrically connects the routing line and the pad.

Abstract: A reinforced solder bump connector structure is formed between a contact pad arranged on a semiconductor chip and a ball pad arranged on a mounting substrate. The semiconductor chip includes at least one reinforcing protrusion extending upwardly from a surface of an intermediate layer. The mounting substrate includes at least one reinforcing protrusion extending upwardly from a ball pad, the protrusions from both the chip and the substrate being embedded within the solder bump connector. In some configurations, the reinforcing protrusion from the contact pad and the ball pad are sized and arranged to have overlapping under portions. These overlapping portions may assume a wide variety of configurations that allow the protrusions to overlap without contacting each other including pin arrays and combinations of surrounding and surrounded elements. In each configuration, the reinforcing protrusions will tend to suppress crack formation and/or crack propagation thereby improving reliability.

Abstract: A method and system for providing at least one contact in a semiconductor device. The semiconductor device includes a substrate, an etch stop layer, an interlayer dielectric on the etch stop layer, an anti-reflective coating layer on the interlayer dielectric, and at least one feature below the etch stop layer. A resist mask having an aperture and residing on the anti-reflective coating layer is provided. The aperture is above an exposed portion of the anti-reflective coating layer. The method and system include etching the exposed anti-reflective coating layer and the underlying interlayer dielectric without etching through the etch stop layer, thereby providing a portion of at least one contact hole. The method and system also include removing the resist mask in situ, removing a portion of the etch stop layer exposed in the portion of the contact hole, and filling the contact hole with a conductive material.

Abstract: The present invention provides a micro-electro-mechanical system (MEMS) device, a method of manufacture therefore, and an optical communications system including the same. The device includes an electrode located over a substrate and a charge dissipation layer located proximate and electrically coupled to the substrate. The device may further include a moveable element located over the electrode.

Abstract: Provided is a semiconductor device comprising a first metal film formed above a semiconductor chip, a ball portion formed over said first metal film and made of a second metal, and an alloy layer of said first metal and said second metal which alloy layer is formed between said first metal film and said ball portion, wherein said alloy layer reaches the bottom of said first metal film, and said ball portion is covered with a resin; and a manufacturing method thereof. The present invention makes it possible to improve adhesion between the bonding pad portion and ball portion of a bonding wire over an interconnect, thereby improving the reliability of the semiconductor device.

Abstract: A method of manufacture of a semiconductor device can speedily peel extremely thin chips which are laminated to an adhesive tape without generating cracks or chippings. In this regard, the head of a vibrator is brought into contact with a back surface of an adhesive tape to which a plurality of semiconductor chips are laminated. By applying longitudinal vibrations having a frequency of 1 kHz to 100 kHz and an amplitude of 1 ?m to 50 ?m, the chip is peeled from the adhesive tape. In applying the longitudinal vibrations to the adhesive tape, a tension in a horizontal direction is applied to the adhesive tape.

Abstract: A nonvolatile semiconductor memory device includes a plurality of memory cells. A couple of bits of data can be stored in the memory cell, the stored data being controlled according to resistance values of first and second variable resistance regions. One of the plurality of memory cells shares its first diffusion layer with an adjacent memory cell and shares its second diffusion layer with another adjacent memory cell. The first diffusion layers of the plurality of memory cells are coupled to each other with a first conductive line extending in a first direction. The second diffusion layers of the plurality of memory cells are coupled to each other with a second conductive line extending in the first direction. The gate electrodes of the plurality of memory cells are coupled to each other with a third conductive line extending in a second direction, which is orthogonal to the first direction.

Abstract: A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23 are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 ?mRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.

Abstract: A method for fabricating organic light-emitting diodes (OLEDs) and OLED displays using screen-printing, where a first electrode, at least one organic material, and a second electrode are formed on a substrate and at least one of the first and second electrodes and the at least one organic material is screen printed by positioning a screen with openings forming a pattern above a substrate and depositing a material onto the substrate through the openings. Exemplary embodiments include fabricating the electrodes and/or the at least one organic material as continuous layers or uniform, discrete blocks on the substrate and fabricating red, green, and blue OLEDs on the same substrate, which are then placed in OLED displays.

Abstract: A method of fabrication of a semiconductor integrated circuit device, calls for disposing, in an ultrapure water preparing system, UF equipment having therein a UF module which has been manufactured by disposing, in a body thereof, a plurality of capillary hollow fiber membranes composed of a polysulfone membrane or polyimide membrane, bonding the plurality of hollow fiber membranes at end portions thereof by hot welding, and by this hot welding, simultaneously adhering the hollow fiber membranes to the body. Upon preparation of ultrapure water to be used for the fabrication of the semiconductor integrated circuit device, it is possible to prevent run-off of ionized amine into the ultrapure water.

Abstract: A process for forming an isolation region comprised of shallow trench-deep trench configuration, wherein a smooth top surface topography is obtained for the isolation region and for adjacent active device regions in the semiconductor substrate, has been developed. The process features initially forming an insulator filled shallow trench shape, planarized via a first chemical mechanical polishing procedure, allowing reduced complexity to be realized during the subsequent formation of a narrow diameter, deep trench opening, in the insulator filled shallow trench shape and in an underlying portion of semiconductor substrate. Formation of a recessed polysilicon plug located in the bottom portion of the deep trench opening is followed by formation of an insulator plug located in a top portion of the deep trench opening, overlying the recessed polysilicon plug.

Abstract: A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

Abstract: A photoresist pattern and a method of fabricating the same make it easy to quickly identify a particular portion of a photolithography process that is responsible for causing process defects. The method of fabricating the photoresist pattern includes forming main patterns having a predetermined critical dimension in device-forming regions of a semiconductor substrate, and forming a plurality of test patterns in scribe regions of the substrate. The scribe regions are defined alongside the device-forming regions and separate the device-forming regions from one another. The test patterns have shapes similar to that of the main patterns. Also, one of the test patterns has a critical dimensions similar to that of the main patterns, and other test patterns have respective critical dimensions that are different from the critical dimension of the main patterns.

Abstract: The present invention provides an improved SRAM cell design. The SRAM cell includes a first active area on oxide in a first conductive well located on a first vertical side of the SRAM cell, a second active area on oxide in a second conductive well located on the first vertical side of the SRAM cell, a third active area on oxide in the first conductive well located on a second vertical side of the SRAM cell, a fourth active area on oxide in the second conductive well located on the second vertical side of the SRAM cell, a first gate located on the first vertical side of the SRAM cell, a second gate located on the second vertical side of the SRAM cell, a first local interconnect connecting the first active area, the second active area, and the second gate via a second EC contact located on the second gate, and a second local interconnect connecting the third active area, the fourth active area, and the first gate via a first EC contact located on the first gate.

Abstract: Inductors are provided in chip assemblies such as in packaged semiconductor chips. The inductors may be incorporated in a chip carrier which forms part of the package, and may include, for example, spiral or serpentine inductors formed from traces on the chip carrier. The chip carrier may include a flap bearing the inductive element, and this flap may be bent to tilt the inductive element out of the plane of the chip carrier to reduce electromagnetic interaction between the inductive element and surrounding electrical components. Other inductors include solenoids formed in part by leads on the chip carrier as, for example, by displacing leads out of the plane of the chip carrier to form loops in vertically-extensive planes transverse to the plane of the chip carrier. Additional features provide trimming of the inductor to a desired inductance value during by breaking or connecting leads during assembly.

Abstract: A semiconductor light emitting device includes an LED chip, a first lead frame on which the LED chip is mounted, a second lead frame electrically connected to the LED chip via a bonding wire, and a resin portion surrounding the circumference of the LED chip, and fastening the first and second lead frames. A metal body is located under the region of the first lead frame where the LED chip is mounted.

Abstract: The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.

Abstract: A method to protect a low-K IMD layer underlying a fuse link during a fuse blowing process including a guarded fuse and method for forming the same including forming a fuse portion comprising two metal fuse interconnect structures and a guard ring comprising a metal interconnect structure surrounding the fuse portion in an uppermost IMD layer comprising a dielectric constant of less than about 3.2; forming a protective metal portion electrically isolated in the uppermost IMD layer to cover at least a portion of an area extending between the fuse portions; forming at least one overlying dielectric insulating layer over the uppermost layer to include extended portions of the fuse portion and the guard ring; and, forming a metal fuse link portion to electrically interconnect the fuse portion wherein the fuse portion overlies at least a portion of the protective metal portion.

Abstract: A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y?0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.