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  • Signal timing for I/O
    Patent number: 7317644
    Abstract: Circuits, methods, and apparatus for ordering the timing of clock and data signals. Programmable delay cells are utilized in a data output cell to control a critical multiple data rate input/output write timing so the output can achieve better performance, such as higher maximum frequency of output (Fmax) performance. The delay cells ensure that critical timing criteria between clock signals and data high and low signals are satisfied so that there is a reduced chance of output glitching.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: January 8, 2008
    Assignee: Altera Corporation
    Inventors: Guu Lin, Stephanie T. Tran, Yen-Fu Lin
  • Electrostatic discharge protection circuit
    Patent number: 7271989
    Abstract: Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: September 18, 2007
    Assignee: Altera Corporation
    Inventors: Cheng-Hsiung Huang, Guu Lin, Shih-Lin S. Lee, Chih-Ching Shih, Irfan Rahim, Stephanie T. Tran
  • Electrostatic discharge protection circuit
    Patent number: 7400480
    Abstract: Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: July 15, 2008
    Assignee: Altera Corporation
    Inventors: Cheng-Hsiung Huang, Guu Lin, Shih-Lin S. Lee, Chih-Ching Shih, Irfan Rahim, Stephanie T. Tran
  • Apparatus and Method for Input/Output Module That Optimizes Frequency Performance in a Circuit
    Publication number: 20100006904
    Abstract: A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are interleaved between the signal pads. A circuit can include a module having signal pads that are configurable to route varying signals between the circuit and at least one external device. The module can also have voltage pads that are configurable to route substantially constant voltages between at least one external device and the circuit. The signal pads can be interleaved between the voltage pads. A module with one or more of these features can achieve ideal performance in both wire bond and flip chip packages with the flexibility of setting a different input/output utilization percentage within the module.
    Type: Application
    Filed: July 13, 2008
    Publication date: January 14, 2010
    Applicant: Altera Corporation
    Inventors: Guu Lin, Yen-Fu Lin, Stephanie T. Tran, Pooyan Khoshkhoo
  • Apparatus and method for input/output module that optimizes frequency performance in a circuit
    Patent number: 8138787
    Abstract: A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are interleaved between the signal pads. A circuit can include a module having signal pads that are configurable to route varying signals between the circuit and at least one external device. The module can also have voltage pads that are configurable to route substantially constant voltages between at least one external device and the circuit. The signal pads can be interleaved between the voltage pads. A module with one or more of these features can achieve ideal performance in both wire bond and flip chip packages with the flexibility of setting a different input/output utilization percentage within the module.
    Type: Grant
    Filed: July 13, 2008
    Date of Patent: March 20, 2012
    Assignee: Altera Corporation
    Inventors: Guu Lin, Yen-Fu Lin, Stephanie T. Tran, Pooyan Khoshkhoo
  • Flexible data strobe signal bus structure for wirebond and flip-chip packaging
    Patent number: 8385142
    Abstract: An integrated circuit with a flexible data strobe signal (DQS) bus structure is presented. The integrated circuit has a number of input/output (I/O) modules with a number of data pins to receive and transmit data. In addition, a subset of the I/O modules also have a data strobe pin. The input/output modules are connected to data strobe signal buses having a fixed configuration. The configuration of the fixed DQS bus groups a number of data pins with a corresponding data strobe pin and the grouping of data pin spans multiple I/O modules. The integrated circuit also has a flexible data bus connected to the I/O modules. Data pins of I/O modules of a second integrated circuit are mapped a subset of the data pins of corresponding I/O modules of the integrated circuit. The flexible data strobe signal bus enables selection of the subset of data pins in the integrated circuit.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: February 26, 2013
    Assignee: Altera Corporation
    Inventors: Guu Lin, Yen-Fu Lin, Mark W. Fiester, Stephanie T. Tran
  • High voltage pump circuit with reduced oxide stress
    Patent number: 6072358
    Abstract: Improved charge pump circuitry that significantly reduces voltage stress on transistor gate oxides is disclosed. The charge pump circuit according to a preferred embodiment of the present invention includes circuitry that biases the otherwise vulnerable transistors in the charge pump circuit such that the voltage across their gate oxide is reduced. The charge pump of the present invention further provides circuitry to reduce leakage current.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: June 6, 2000
    Assignee: Altera Corporation
    Inventors: Chuan-Yung Hung, John Costello, Stephanie Tran, Guu Lin, Mark Fiester
  • Charge pump circuits and methods
    Patent number: 6774707
    Abstract: Charge pump circuits and methods of the present invention step up an input voltage to provide an output voltage. The charge pump circuits have one or more stages. Each stage may include a capacitor and a transistor. Each stage adds an incremental voltage to an input voltage. The capacitors elevate the voltage at a terminal of the transistors in each stage in response to a clock signal to provide the incremental voltage. The output voltage is the sum of the input voltage and the incremental voltages provided by each stage. One or more of the stages of the charge pump circuit may have a depletion transistor. Depletion transistors may be field-effect transistors that have a lower threshold voltage as a result of an implant in the channel region of the device.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: August 10, 2004
    Assignee: Altera Corporation
    Inventors: Mian Smith, Myron Wong, Guu Lin, Stephanie Tran
  • Flexible macrocell interconnect
    Patent number: 7573297
    Abstract: Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: August 11, 2009
    Assignee: Altera Corporation
    Inventors: Guu Lin, Stephanie Tran, Bruce Pederson, Brad Vest, Jim Park, Jay Schleicher
  • Flexible macrocell interconnect
    Patent number: 6927601
    Abstract: Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 9, 2005
    Assignee: Altera Corporation
    Inventors: Guu Lin, Stephanie Tran, Bruce Pederson, Brad Vest, Jim Park, Jay Schleicher
  • Flexible macrocell interconnect
    Patent number: 7161384
    Abstract: Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: January 9, 2007
    Assignee: Altera Corporation
    Inventors: Guu Lin, Stephanie Tran, Bruce Pederson, Brad Vest, Jim Park, Jay Schleicher
  • ESD protection that supports LVDS and OCT
    Patent number: 7250660
    Abstract: Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: July 31, 2007
    Assignee: Altera Corporation
    Inventors: Cheng-Hsiung Huang, Chih-Ching Shih, Jeffrey Tyhach, Guu Lin, Chiakang Sung, Stephanie T. Tran
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