Abstract: The present disclosure advantageously provides an Optical Hardware Accelerator (OHA) for an Artificial Neural Network (ANN) that includes a communication bus interface, a memory, a controller, and an optical computing engine (OCE). The OCE is configured to execute an ANN model with ANN weights. Each ANN weight includes a quantized phase shift value ?i and a phase shift value ?i. The OCE includes a digital-to-optical (D/O) converter configured to generate input optical signals based on the input data, an optical neural network (ONN) configured to generate output optical signals based on the input optical signals, and an optical-to-digital (O/D) converter configured to generate the output data based on the output optical signals. The ONN includes a plurality of optical units (OUs), and each OU includes an optical multiply and accumulate (OMAC) module.
Type:
Application
Filed:
March 13, 2020
Publication date:
September 16, 2021
Applicant:
Arm Limited
Inventors:
Zhi-Gang Liu, Matthew Mattina, John Fremont Brown, III
Abstract: The present disclosure advantageously provides an Optical Hardware Accelerator (OHA) for an Artificial Neural Network (ANN) that includes a communication bus interface, a memory, a controller, and an optical computing engine (OCE). The OCE is configured to execute an ANN model with ANN weights. Each ANN weight includes a quantized phase shift value ?i and a phase shift value ?i. The OCE includes a digital-to-optical (D/O) converter configured to generate input optical signals based on the input data, an optical neural network (ONN) configured to generate output optical signals based on the input optical signals, and an optical-to-digital (O/D) converter configured to generate the output data based on the output optical signals. The ONN includes a plurality of optical units (OUs), and each OU includes an optical multiply and accumulate (OMAC) module.
Type:
Grant
Filed:
March 13, 2020
Date of Patent:
December 13, 2022
Assignee:
Arm Limited
Inventors:
Zhi-Gang Liu, Matthew Mattina, John Fremont Brown, III
Abstract: An all-photonic computational accelerator encodes information in the amplitudes of frequency modes stored in a ring resonator. Nonlinear optical processes enable interaction among these modes. Both the matrix multiplication and element-wise activation functions on these modes (the artificial neurons) occur through coherent processes, enabling the representation of negative and complex numbers without digital electronics. This accelerator has a lower hardware footprint than electronic and optical accelerators, as the matrix multiplication happens in a single multimode resonator on chip. Our architecture provides a unitary, reversible mode of computation, enabling on-chip analog Hamiltonian-echo backpropagation for gradient descent and other self-learning tasks. Moreover, the computational speed increases with the power of the pumps to arbitrarily high rates, as long as the circuitry can sustain the higher optical power.
Type:
Application
Filed:
May 2, 2023
Publication date:
November 2, 2023
Inventors:
Jasvith Raj Basani, Mikkel HEUCK, Dirk Robert ENGLUND, Stefan Ivanov Krastanov