Search Patents
  • Ultrasonic transducer array and imaging system
    Patent number: 3979711
    Abstract: An ultrasonic bidirectional transducer array, and an imaging system including said array, wherein the array comprises a plurality of transducer elements each having a major face capable of bidirectionally transmitting and receiving ultrasonic energy and an opposite face. The transducer elements have their major bidirectional faces arrayed in a predetermined surface. Means is carried by the opposite face of each element for bidirectionally providing and receiving electrical energy across each transducer element. In the imaging system the array may be selectively scanned to provide successive displays of moving objects at a rate which gives the impression of continuous motion to a human observer.
    Type: Grant
    Filed: June 17, 1974
    Date of Patent: September 7, 1976
    Assignee: The Board of Trustees of Leland Stanford Junior University
    Inventors: Maxwell G. Maginness, James D. Meindl, James D. Plummer
  • Negative differential resistance devices and approaches therefor
    Patent number: 7508701
    Abstract: Negative differential resistance devices are implemented to facilitate current flow under different operating conditions. According to an example embodiment of the present invention, an NDR device is arranged for selective passage of current through relatively high tunneling efficiency regions and relatively low tunneling efficiency regions. In some applications, a gate is used to accumulate carriers to facilitate the passage of current that is predominantly one of tunneling current and generation current, respectively, by controlling the passage of current through a relatively high tunneling efficiency region and a relatively low tunneling efficiency region. In some implementations, the NDR device is arranged to mitigate leakage in a storage device using a two-terminal connection.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: March 24, 2009
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Yue Liang, Kailash Gopalakrishnan, Peter Griffin, James D. Plummer
  • Crystalline-type device and approach therefor
    Patent number: 7498243
    Abstract: Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material is crystallized to form the single-crystal region using an approach involving defect inhibition for the promotion of single-crystalline growth. In some instances, this defect inhibition involves the reduction and/or elimination of defects using a relatively small physical opening via which a crystalline growth front propagates. In other instances, this defect inhibition involves causing a change in crystallization front direction relative to a crystallization seed location.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: March 3, 2009
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Yaocheng Liu, Michael D. Deal, James D. Plummer
  • SINGLE METAL CRYSTALS
    Publication number: 20170121843
    Abstract: A single-crystalline metal is created on a substrate by liquefying a metal material contained within a crucible while in contact with a surface of the substrate, cooling the metal material by causing a temperature gradient effected in the substrate in a direction that is neutral along the surface of the substrate and, therein, growing the single-crystalline metal in the crucible.
    Type: Application
    Filed: October 31, 2016
    Publication date: May 4, 2017
    Inventors: James D. Plummer, Kai Zhang, Xue Bai Pitner, Jonathan A. Fan
  • Single metal crystals
    Patent number: 10435814
    Abstract: A single-crystalline metal is created on a substrate by liquefying a metal material contained within a crucible while in contact with a surface of the substrate, cooling the metal material by causing a temperature gradient effected in the substrate in a direction that is neutral along the surface of the substrate and, therein, growing the single-crystalline metal in the crucible.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: October 8, 2019
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: James D. Plummer, Kai Zhang, Xue Bai Pitner, Jonathan A. Fan
  • Two-dimensional bulk acoustic wave correlator-convolver
    Patent number: 4523293
    Abstract: A two-dimensional bulk acoustic wave correlator-convolver having an acoustic mirror positioned two focal lengths from an integrated circuit-acoustic transducer array. The image, rather than the Fourier transform, of the input spatial distribution is returned to the transducer array by the mirror.
    Type: Grant
    Filed: April 5, 1983
    Date of Patent: June 11, 1985
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Bert A. Auld, Donald W. Pettibone, James D. Plummer
  • Double heterojunction inversion base transistor
    Patent number: 4825269
    Abstract: A bipolar transistor in which the base region includes a heterostructure and a doped layer of semiconductor material with the heterostructure functioning as a two-dimensional hole gas. The doped layer is sufficiently thin to prevent occurrence of a charge-neutral region of holes. In operation the transistor can switch quickly since minority charge storage in the base region does not present a problem. The device lends itself to downscaling in size in a VLSI circuit.
    Type: Grant
    Filed: March 4, 1988
    Date of Patent: April 25, 1989
    Assignee: Stanford University
    Inventors: James D. Plummer, Robert C. Taft
  • Methods for forming lateral and vertical DMOS transistors
    Patent number: 4682405
    Abstract: A transistor is provided which includes an electrical contact (122) formed in a V-shaped groove (118). Because of the unique shape of the electrical contact, a smaller surface area is required for its formation thus rendering it possible to construct a transistor having a smaller surface area. The groove is formed by anisotropically etching an expitaxial layer (102) on a semiconductor substrate (100) using, for example, KOH.
    Type: Grant
    Filed: July 22, 1985
    Date of Patent: July 28, 1987
    Assignee: Siliconix Incorporated
    Inventors: Richard A. Blanchard, James D. Plummer
  • Thyristor-based semiconductor device and method of fabrication
    Patent number: 7195959
    Abstract: A thyristor-based semiconductor memory device may comprise at least a region thereof, e.g., a p-base region, having high ionization energy impurity, such as a dopant. This high ionization energy impurity within a base region may be operable to compensate for a gain-versus-temperature dependence of a constituent bipolar transistor of the thyristor element of a thyristor-based memory device. In particular embodiments, the high ionization energy impurity may include a donor and/or acceptor in silicon.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: March 27, 2007
    Assignee: T-Ram Semiconductor, Inc.
    Inventors: James D. Plummer, Zachary K. Lee, Kevin J. Yang, Farid Nemati
  • Monolithic semiconductor switching device
    Patent number: 4199774
    Abstract: An electrical circuit device made in integrated monolithic form has low level operating characteristics of a MOS device and high level operating characteristics of a Triac. The structure includes two double diffused MOS transistors which have merged drain regions. At higher voltage and current levels a lateral Triac structure is triggered by the MOS devices. Alternatively, separate terminal contacts can be made to the P and N regions comprising the MOS transistor source and channel regions with the Triac triggered conventionally by an externally applied control voltage.
    Type: Grant
    Filed: September 18, 1978
    Date of Patent: April 22, 1980
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventor: James D. Plummer
  • Thyristor-based semiconductor device with indium-carbon implant and method of fabrication
    Patent number: 7592642
    Abstract: A thyristor-based memory device may comprise two base regions of opposite type conductivity formed between a cathode-emitter region and an anode-emitter region. A junction defined between the p-base region and the cathode-emitter region of the thyristor may be “treated” with a high ionization energy acceptor such as indium in combination with carbon as an activation assist species. These two implants may form complexes that may extend across the junction region.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: September 22, 2009
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Srinivasa R. Banna, James D. Plummer
  • THYRISTOR DEVICE WITH CARBON LIFETIME ADJUSTMENT IMPLANT AND ITS METHOD OF FABRICATION
    Publication number: 20090162979
    Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
    Type: Application
    Filed: February 9, 2009
    Publication date: June 25, 2009
    Inventors: Kevin J. Yang, Farid Nemati, Scott Robins, James D. Plummer, Hyun-Jin Cho
  • Thyristor device with carbon lifetime adjustment implant and its method of fabrication
    Patent number: 7488626
    Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: February 10, 2009
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Kevin J. Yang, Farid Nemati, Scott Robins, James D. Plummer, Hyun-Jin Cho
  • Thyristor device with carbon lifetime adjustment implant and its method of fabrication
    Patent number: 7858449
    Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: December 28, 2010
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Kevin J. Yang, Farid Nemati, Scott Robins, James D. Plummer, Hyun-Jin Cho
  • Thyristor device with carbon lifetime adjustment implant and its method of fabrication
    Patent number: 7075122
    Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: July 11, 2006
    Assignee: T-Ram Semiconductor, Inc.
    Inventors: Kevin J. Yang, Farid Nemati, Scott Robins, James D. Plummer, Hyun-Jin Cho
  • Thyristor-type memory device
    Publication number: 20040159853
    Abstract: A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
    Type: Application
    Filed: February 12, 2004
    Publication date: August 19, 2004
    Inventors: Farid Nemati, James D. Plummer
  • Thyristor-type memory device
    Patent number: 6967358
    Abstract: A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: November 22, 2005
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Farid Nemati, James D. Plummer
  • Thyristor-type memory device
    Patent number: 7365373
    Abstract: A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: April 29, 2008
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Farid Nemati, James D. Plummer
  • Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches
    Patent number: 6229161
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: May 8, 2001
    Assignee: Stanford University
    Inventors: Farid Nemati, James D. Plummer
  • Monolithic semiconductor switching device
    Patent number: RE33209
    Abstract: An electrical circuit device made in integrated monolithic form has low level operating characteristics of a MOS device and high level operating characteristics of a Triac. The structure includes two double diffused MOS transistors which have merged drain regions. At higher voltage and current levels a lateral Triac structure is triggered by the MOS devices. Alternatively, separate terminal contacts can be made to the P and N regions comprising the MOS transistor source and channel regions with the Triac triggered conventionally by an externally applied control voltage.
    Type: Grant
    Filed: December 5, 1983
    Date of Patent: May 1, 1990
    Assignee: Board of Trustees of the Leland Stanford Jr. Univ.
    Inventor: James D. Plummer
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