Search Patents
  • Monolithic semiconductor switching device
    Patent number: 4199774
    Abstract: An electrical circuit device made in integrated monolithic form has low level operating characteristics of a MOS device and high level operating characteristics of a Triac. The structure includes two double diffused MOS transistors which have merged drain regions. At higher voltage and current levels a lateral Triac structure is triggered by the MOS devices. Alternatively, separate terminal contacts can be made to the P and N regions comprising the MOS transistor source and channel regions with the Triac triggered conventionally by an externally applied control voltage.
    Type: Grant
    Filed: September 18, 1978
    Date of Patent: April 22, 1980
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventor: James D. Plummer
  • Boat transport device
    Patent number: 12017740
    Abstract: The present invention relates generally to the field of boat transports or carriers which may be mounted to a sidewall of the boat by a bracket. The carrier has a frame and a wheel assembly that has a horizontal cross member, a first vertical fork, a second vertical fork, a mounting bracket and a wheel. An individual may place two boat-mounted brackets on to opposing sides of a boat, so that the user may easily wheel the boat to the desired location. Once at the location, the user can then remove each wheel assembly and use the boat as normal.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: June 25, 2024
    Inventors: James Plummer, Penny Ramstein
  • Two-dimensional bulk acoustic wave correlator-convolver
    Patent number: 4523293
    Abstract: A two-dimensional bulk acoustic wave correlator-convolver having an acoustic mirror positioned two focal lengths from an integrated circuit-acoustic transducer array. The image, rather than the Fourier transform, of the input spatial distribution is returned to the transducer array by the mirror.
    Type: Grant
    Filed: April 5, 1983
    Date of Patent: June 11, 1985
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Bert A. Auld, Donald W. Pettibone, James D. Plummer
  • Thyristor-type memory device
    Patent number: 7365373
    Abstract: A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: April 29, 2008
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Farid Nemati, James D. Plummer
  • Thyristor-type memory device
    Patent number: 6967358
    Abstract: A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: November 22, 2005
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Farid Nemati, James D. Plummer
  • Negative differential resistance devices and approaches therefor
    Patent number: 7508701
    Abstract: Negative differential resistance devices are implemented to facilitate current flow under different operating conditions. According to an example embodiment of the present invention, an NDR device is arranged for selective passage of current through relatively high tunneling efficiency regions and relatively low tunneling efficiency regions. In some applications, a gate is used to accumulate carriers to facilitate the passage of current that is predominantly one of tunneling current and generation current, respectively, by controlling the passage of current through a relatively high tunneling efficiency region and a relatively low tunneling efficiency region. In some implementations, the NDR device is arranged to mitigate leakage in a storage device using a two-terminal connection.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: March 24, 2009
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Yue Liang, Kailash Gopalakrishnan, Peter Griffin, James D. Plummer
  • Semiconductor capacitively-coupled NDR device and related applications in high-density high-speed memories and in power switches
    Patent number: 6727529
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: April 27, 2004
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Farid Nemati, James D. Plummer
  • Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches
    Patent number: 6229161
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: May 8, 2001
    Assignee: Stanford University
    Inventors: Farid Nemati, James D. Plummer
  • Manufacture of semiconductor capacitively-coupled NDR device for applications such as high-density high-speed memories and power switches
    Publication number: 20020096690
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
    Type: Application
    Filed: March 20, 2002
    Publication date: July 25, 2002
    Applicant: Stanford University
    Inventors: Farid Nemati, James D. Plummer
  • Semiconductor capacitively-coupled NDR device and related applications in high-density high-speed memories and in power switches
    Publication number: 20020096689
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
    Type: Application
    Filed: March 20, 2002
    Publication date: July 25, 2002
    Applicant: Stanford University
    Inventors: Farid Nemati, James D. Plummer
  • Thyristor-type memory device
    Publication number: 20040159853
    Abstract: A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
    Type: Application
    Filed: February 12, 2004
    Publication date: August 19, 2004
    Inventors: Farid Nemati, James D. Plummer
  • Manufacture of semiconductor capacitively-coupled NDR device for applications such as high-density high-speed memories and power switches
    Patent number: 6528356
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: March 4, 2003
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Farid Nemati, James D. Plummer
  • Semiconductor current-switching device having operational enhancer and method therefor
    Patent number: 6448586
    Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other type of NDR-based SRAMs.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: September 10, 2002
    Assignee: The Board of Trustees of the Leland Standford Junior University
    Inventors: Farid Nemati, James D. Plummer
  • Stopper
    Patent number: D255429
    Type: Grant
    Filed: May 1, 1978
    Date of Patent: June 17, 1980
    Assignee: Owens-Illinois, Inc.
    Inventor: James E. Plummer
  • Stopper
    Patent number: D255660
    Type: Grant
    Filed: September 13, 1978
    Date of Patent: July 1, 1980
    Assignee: Owens-Illinois, Inc.
    Inventor: James E. Plummer
  • Stopper
    Patent number: D257230
    Type: Grant
    Filed: March 21, 1979
    Date of Patent: October 7, 1980
    Assignee: Owens-Illinois, Inc.
    Inventor: James E. Plummer
  • Combined bottle and stopper
    Patent number: D258935
    Type: Grant
    Filed: March 21, 1979
    Date of Patent: April 21, 1981
    Assignee: Owens-Illinois, Inc.
    Inventor: James E. Plummer
  • Pitcher
    Patent number: D259091
    Type: Grant
    Filed: March 21, 1979
    Date of Patent: May 5, 1981
    Assignee: Owens-Illinois, Inc.
    Inventor: James E. Plummer
  • Combined decanter and stopper
    Patent number: D260365
    Type: Grant
    Filed: September 13, 1978
    Date of Patent: August 25, 1981
    Assignee: Owens-Illinois, Inc.
    Inventor: James E. Plummer
  • Monolithic semiconductor switching device
    Patent number: RE33209
    Abstract: An electrical circuit device made in integrated monolithic form has low level operating characteristics of a MOS device and high level operating characteristics of a Triac. The structure includes two double diffused MOS transistors which have merged drain regions. At higher voltage and current levels a lateral Triac structure is triggered by the MOS devices. Alternatively, separate terminal contacts can be made to the P and N regions comprising the MOS transistor source and channel regions with the Triac triggered conventionally by an externally applied control voltage.
    Type: Grant
    Filed: December 5, 1983
    Date of Patent: May 1, 1990
    Assignee: Board of Trustees of the Leland Stanford Jr. Univ.
    Inventor: James D. Plummer
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