Abstract: Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems. In embodiments, the color based track systems can include irregularly spaced and non-uniform width colored tracks. These and other embodiments include a methodology to automatically generate a track pattern for an integrated circuit design that satisfies both design constraints and user inputs. Various alternatives for identifying starting points in the design for automatically generating track patterns are possible.
Type:
Grant
Filed:
February 6, 2017
Date of Patent:
October 22, 2019
Assignee:
CADENCE DESIGN SYSTEMS, INC.
Inventors:
Sabra Rossman, Gary Matsunami, Karun Sharma, Steven Riley, Joshua A. Baudhuin
Abstract: Disclosed are techniques for implementing routing aware floorplanning or placement for an electronic design. These techniques preprocess an electronic design and a plurality of inputs for a floorplanner or placer, identify a tentative location for inserting a block comprising one or more pins into a floorplan or placement layout, snap the block to a legal location based at least in part upon one or more characteristics of the one or more pins or one or more pseudo-pins, and update the floorplan or placement layout with one or more geometric routes based in part or in whole upon the legal location.
Type:
Grant
Filed:
June 29, 2017
Date of Patent:
December 24, 2019
Assignee:
Cadence Design Systems, Inc.
Inventors:
Roland Ruehl, Henry Yu, Joshua Alexander Baudhuin