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  • LEAD BIDDING SYSTEM AND METHOD
    Publication number: 20140074552
    Abstract: A lead bidding system and methods allows users to bid on leads based on dynamically qualified electronically transmissible documents and dissemination of those leads. The system and methods reduce the barrier to conversion associated with interacting with electronically transmissible documents and also provides a technique to create customized leads.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 13, 2014
    Applicant: Madison Logic, Inc.
    Inventors: Eric Matlick, Cynthia Hyunh, Vincent Henri Lucien Turk, Tai Denh Mong
  • SYSTEM AND METHOD FOR ASSET INTEREST DETERMINATION
    Publication number: 20140074773
    Abstract: A system for generating applicable electronically transmissible documents includes an applicability service that determines electronically transmissible documents from an electronically transmissible document reference library that are most likely to result in revenues when provided to the user of a website. The applicability service may determine the applicable electronically transmissible documents based upon a number of specifications provided by a website publisher, the electronically transmissible document provider, an electronically transmissible document owner, and/or the user accessing the website.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 13, 2014
    Applicant: Madison Logic, Inc.
    Inventors: Eric Matlick, Oleg Khavronin, Vincent Henri Lucien Turk, Eugene Livchits
  • Logic simulator
    Patent number: 5910901
    Abstract: A logic simulator, which is capable of running logic simulations in a short period of time by eliminating operations relating to portions of a logic circuit which have previously been developed. A simulation performing section runs a logic simulation based on a net list and an input test vector, and outputs an output test vector which expresses the results. A macro generating section generates ROM code for a ROM equivalent to the logic circuit being simulated based on the input test vector and the output test vector, and stores this as a ROM macro. When the net list references the ROM macro in subsequent logic simulations, the simulation performing section refers to the ROM code of the ROM macro.
    Type: Grant
    Filed: January 15, 1997
    Date of Patent: June 8, 1999
    Assignee: Yamaha Corporation
    Inventor: Naoki Yamada
  • Data storage apparatus having memory area with a predetermined logic type
    Patent number: 5644750
    Abstract: A data memory of an IC card is divided into a plurality of areas, a logic type used when data is written in each area is set, and the logical AND between the written data and stored data in the memory is calculated by an AND logic circuit and written in the memory. In read access, output data can be directly obtained from the memory.
    Type: Grant
    Filed: March 22, 1994
    Date of Patent: July 1, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuo Iijima
  • Gunn transceiver logic input circuit for use in a semiconductor memory device
    Patent number: 5680062
    Abstract: A gunn transceiver logic input circuit for use in a semiconductor memory device is capable of effectively inputting a signal having a small voltage difference. The gunn transceiver logic input circuit includes first and second input units which respectively input a GTL-level input signal and a GTL-level reference signal. First and second generating units with first and second level shifters respectively shift the GTL-level input signal and GTL-level reference signal to the ECL-level. An ECL buffer circuit compares the voltages between the ECL-level input signal and the ECL-level reference signal and generates first and second ECL-level output signals while maintaining a swing width of the GTL level signal.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: October 21, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-dae Lee, Chul-min Jung, Uk-rae Cho
  • Logic circuit controlled by a plurality of clock signals
    Patent number: 6046607
    Abstract: A semiconductor integrated circuit has an integrally formed logic circuit that is controlled by clock signals. The semiconductor integrated circuit includes a clock signal delay device that generates a plurality of clock signals having phases that are shifted from each other by a small amount with respect to a reference clock signal. The logic circuit is divided into a plurality (N number) of circuit blocks so that each of the circuit blocks is controlled by each of the associated plurality of clock signals to reduce noises. Noises in a CMOS integrated circuit are also reduced by controlled reference clock signals. A CMOS integrated circuit includes at least one CMOS gate with an input terminal being commonly connected to gates of a PMOS transistor and an NMOS transistor, and a latch circuit for transmitting data to the input terminal of the CMOS gate by clock signal control.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: April 4, 2000
    Assignee: Yamaha Corporation
    Inventor: Takayuki Kohdaka
  • Pipeline arithmetic and logic system with clock control function for selectively supplying clock to a given unit
    Patent number: 5771376
    Abstract: A pipeline arithmetic and logic system capable of adjusting operational timings among stages without using an NOP instruction, providing a size reduction of its control section. The system has a decoder set including decoder groups divided into a decoder group for controlling an arithmetic section unit, a register file unit and a program counter unit, and a decoder for control of an address unit, and further including a clock control unit controlled by the address unit control decoder. A clock signal from an external source is directly fed to the address unit while being fed through the clock control unit to the other units. When fetching a data transfer instruction and repeatedly executing an MA stage twice, the system stops the clock control unit at the execution of the first MA stage to inhibit the operations of the units other than the address unit.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: June 23, 1998
    Assignee: Nippondenso Co., Ltd
    Inventors: Hiroshi Hayakawa, Harutsugu Fukumoto, Hiroaki Tanaka
  • Method and system of providing subscriber-specified service by an intelligent network
    Patent number: 6003031
    Abstract: The invention relates to a method of providing a subscriber-specific service by an intelligent network. In the method, a service logic program is stored in a database (BD1, DB2) of the intelligent network and a subscriber-specific service is provided by starting said service logic program in response to a predefined trigger condition. In order that subscriber-specific services could be implemented economically on a really large scale, (a) the service logic program is implemented as a service logic program (400) common to a plurality of subscribers, (b) subscriber-specific information relating to the service is stored, for each subscriber, separately from said service logic program, and (c) in the service logic program there are defined points from which the program reads, during the execution, subscriber-specific information on an individual subscriber, whereby the execution of the common service logic program with the read subscriber-specific information provides said subscriber-specific service.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: December 14, 1999
    Assignee: Nokia Telecommunications Oy
    Inventors: Eeva Hartikainen, Asko Suorsa, Leena Sivola
  • Semiconductor integrated device
    Patent number: 5805605
    Abstract: A semiconductor integrated device is disclosed which is capable of selectively executing a memory test and a logic test. The device includes a logic part for realizing a plurality of operation functions in logic, a memory part having a given integration and for storing data, a pad part including a pad for inputting/outputting a control signal according to respective tests, a switch part respectively connected to the logic part, the memory part, and the pad part, and a switch control part for controlling the switch part to thereby selectively control the memory test and the logic test. The semiconductor integrated device according to the present invention is capable of performing a separate logic test by dividing a memory fault and a logic fault on a memory testing path. The semiconductor integrated device has a memory signal path, a logic signal path, and a pad path which are selectively used.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: September 8, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheol-Ha Lee, Myung-Ho Bae
  • Method and apparatus for processing picture elements
    Patent number: 6088033
    Abstract: A pixel processing apparatus receives pixels from an external source (100) and stores them in a storage area (110). A data path (120) performs mathematical operations and tests whether or not a pixel is to be suppressed. For an effective memory access, a control logic (130) provides addresses to the storage area (110). The control logic (130) receives status data from the data path (120), indicating whether or not a pixel is to be suppressed and modifies the status register (140) accordingly. The control logic (130) prevents the data path (120) from performing further operations on a pixel if the status register (140) indicates that the pixel is to be suppressed. Preferably, the control logic suppresses address generation for the location of the pixel in question if said status register (140) indicates that the pixel is to be suppressed.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: July 11, 2000
    Assignee: VLSI Solution Oy
    Inventor: Eero Pajarre
  • Apparatus for flexibly selecting primary and secondary connectors and master and slave cascaded disk drives of an IDE interface
    Patent number: 5649233
    Abstract: An apparatus for selecting the primary/secondary and the master/slave configuration of an enhanced IDE interface. The apparatus has a first and a second connector, each for connecting to a cascade of a first and a second IDE drive device. The apparatus comprises a primary/secondary configuration logic and a master/slave configuration logic. The primary/secondary configuration logic is utilized for selectively configuring the first and second connectors of the enhanced IDE interface as the primary and secondary connectors of the IDE interface respectively, or as the secondary and primary connectors of the enhanced IDE interface respectively. The master/slave configuration logic is utilized for selectively configuring the first and second IDE drive devices in each of the cascades as the master and slave drives respectively, or as the slave and master drives respectively.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: July 15, 1997
    Assignee: United Microelectronics Corporation
    Inventor: Zhi-Hsien Chen
  • System for handling an asynchronous interrupt a universal serial bus device
    Patent number: 6085265
    Abstract: A system and method for establishing communication between a host computer and a peripheral device. The host computer includes logic for associating an attached peripheral device with one of a particular peripheral device type, logic for associating the attached peripheral device with an instance of a software driver executable on the processor, and logic for enabling communication between the attached device and the host after a set period of time after detection of the attachment of the USB device to the at least one port. The software driver is preferably capable of supporting communication between peripheral devices of the associated particular type and the host.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: July 4, 2000
    Assignee: Toshiba America Information Systems, Inc.
    Inventor: James Tai-Ling Kou
  • Location Determination With A Wireless System
    Publication number: 20070254674
    Abstract: A mobile device comprises host logic and a first transceiver coupled to the host logic. The first transceiver is adapted to wirelessly communicate with a second transceiver. The second transceiver is positioned at a fixed location and comprises location information indicative of such fixed location. The first transceiver transmits wireless beacon signals. When the second transceiver is within range of the first transceiver, the beacon signal automatically causes the second transceiver to transmit the location information to the first transceiver.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 1, 2007
    Applicant: Texas Instruments, Inc.
    Inventors: Madison Pedigo, Carl Panasik
  • Programming switch for non-volatile memory
    Patent number: 5682348
    Abstract: The object of present invention is to provide a programming switch for non-volatile memory wherein output voltage Vout versus input voltage Vin satisfies the following relations: (1) While Vin is logic "0", Vout is logic "0"; (2) While Vin is logic "1", Vout is about the value of programming voltage Vpp if programming is executed and about the value of supply voltage Vcc if programming is not executed. The present invention is characterized in that it can be utilized in general non-volatile memory and the supply voltage needed can be as low as 2 volts, resulting in body effect almost giving no influence.
    Type: Grant
    Filed: April 9, 1996
    Date of Patent: October 28, 1997
    Assignee: Myson Technology, Inc.
    Inventors: Yi-Pin Lin, Teng Tsai Lin
  • Decryptor
    Patent number: 5790666
    Abstract: A decryptor includes a descrambler for descrambling the scrambled signals using a PN signal, a PN generator which shifts the state successively from its initial state setup by a scramble-key, generates PN signals based on a conversion logic at the shifted state and is capable of changing PNG altering information for generating PN signals and a controller for decrypting a scramble-key from the scrambled signal and giving information for specifying a scramble-key and PN signal generating logic.
    Type: Grant
    Filed: January 18, 1996
    Date of Patent: August 4, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinichi Ooi
  • Clock recovery circuit
    Patent number: 6002279
    Abstract: A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: December 14, 1999
    Assignee: G2 Networks, Inc.
    Inventors: William P. Evans, Eric Naviasky, Patrick Farrell, Anthony Caviglia, John Ebner, Hugh Thompson, Hao Tang
  • Layout designing method for semiconductor integrated circuits
    Patent number: 6195787
    Abstract: A method of designing a layout of a semiconductor integrated circuit is provided. A logic simulation of a semiconductor integrated circuit to be designed is executed. A number of times of toggle operation of each of circuit elements constituting the semiconductor integrated circuit, which occurs during the execution of the logic simulation, is counted. A consumption power of the each of the circuit elements, determined based on the counted number of times of toggle operation thereof. Constraint conditions to be imposed on designing a layout of the circuit elements, are determined based on results of the estimation of the consumption power.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: February 27, 2001
    Assignee: Yamaha Corporation
    Inventor: Moto Yokoyama
  • Expandable arbitration architecture for sharing system memory in a computer system
    Patent number: 5740381
    Abstract: An arbitration bus is arranged between a core logic chip set and a plurality of peripheral devices in order to arbitrate requests by the peripheral devices to use system memory of a computer system. Three or two arbitration signals carried on the arbitration bus. Means are provided to differentiate two levels of priority in each peripheral device. The core logic chip set can make a response pressing or otherwise so as to promote the overall performance. Preemption is provided so that peripheral devices can be overridden without wasting time when it is necessary to do so. Each peripheral device outputs a row address strobe (RAS) signal, all of which are connected together to form a open-collector signal to the core logic chip set for automatically accessing corresponding memory banks of system memory.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: April 14, 1998
    Assignee: United Microelectronics Corporation
    Inventor: Chih-Chan Yen
  • Simulation apparatus and simulation method for semiconductor integrated circuit
    Patent number: 5872724
    Abstract: A simulation apparatus for a semiconductor integrated circuit is provided that includes model preparing device, logic simulating device and power supply voltage drop simulating device. The model preparing device prepares a feeder system model including current sources that correspond to respective circuit elements constituting a circuit to be designed, and power supply wiring and ground wiring for applying voltage to the current sources, on the basis of a result of automatic layout of the circuit. The logic simulating device implements logic simulation of the circuit, and outputs event information related to the circuit elements which have undergone a change of a condition thereof. The power supply voltage drop simulating device implements simulation while driving the current sources in the feeder system model that correspond to the circuit elements listed in the event information, and computing voltage drop in the power supply wiring and the ground wiring.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: February 16, 1999
    Assignee: Yamaha Corporation
    Inventor: Masami Nakada
  • Input protection circuit and method for semiconductor memory device
    Patent number: 5717354
    Abstract: An input protection circuit for a semiconductor memory device senses when the level of an external input signal drops below a reference voltage corresponding to a predetermined logic level, thereby enabling instant correction. The input protection circuit is interposed between an external power voltage terminal and an input terminal of the input buffer, and the external power voltage is transferred to the input terminal of the input buffer when the level of the external input signal applied to the input terminal drops below the predetermined logic level. The circuit includes an internal reference voltage generator which supplies a voltage having a level corresponding to the predetermined logic level and designed to compensate for a known device offset so that the external input signal applied to the input terminal can be instantly corrected.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: February 10, 1998
    Assignee: Samsung Electronics Co., LTD.
    Inventors: Myung-Jae Kim, Do-Chan Choi
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