Search Patents
  • Lateral stack of cobalt and a cobalt-semiconductor alloy for control gate electrodes in a memory structure
    Patent number: 9646975
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers through the backside trench selective to the insulating layers. A cobalt portion is formed in each backside recess. A cobalt-semiconductor alloy portion can be formed on each cobalt portion by depositing a semiconductor material layer on the cobalt portions and reacting the semiconductor material with surface regions of the cobalt portions. A residual portion of the cobalt-semiconductor alloy formed above the alternating stack can be removed by an anisotropic etch or by a planarization process. A combination of a cobalt portion and a cobalt-semiconductor alloy portion within each backside recess can be employed as a word line of a three-dimensional memory device.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: May 9, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Somesh Peri, Sateesh Koka, Raghuveer S. Makala
  • LATERAL STACK OF COBALT AND A COBALT-SEMICONDUCTOR ALLOY FOR CONTROL GATE ELECTRODES IN A MEMORY STRUCTURE
    Publication number: 20170084618
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers through the backside trench selective to the insulating layers. A cobalt portion is formed in each backside recess. A cobalt-semiconductor alloy portion can be formed on each cobalt portion by depositing a semiconductor material layer on the cobalt portions and reacting the semiconductor material with surface regions of the cobalt portions. A residual portion of the cobalt-semiconductor alloy formed above the alternating stack can be removed by an anisotropic etch or by a planarization process. A combination of a cobalt portion and a cobalt-semiconductor alloy portion within each backside recess can be employed as a word line of a three-dimensional memory device.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 23, 2017
    Inventors: Somesh PERI, Sateesh KOKA, Raghuveer S. MAKALA
  • Method of making self-assembling floating gate electrodes for a three-dimensional memory device
    Patent number: 9806089
    Abstract: Metal floating gate electrodes can be formed for a three-dimensional memory device by forming a memory opening having lateral recesses at levels of spacer material layers between insulating layers, depositing a continuous metal layer, and inducing diffusion and agglomeration of the metal into the lateral recesses to form discrete metal portions employing an anneal process. The metallic material can migrate and form the discrete metal portions due to surface tension, which operates to minimize the surface area of the metallic material. Optionally, two or more continuous metal layers can be employed to form discrete metal portions including at least two metals. Optionally, a selective metal deposition process can be performed to deposit additional metal portions including a different metallic material on the discrete metal portions. The metal floating gate electrodes can be formed without employing an etch process. A tunneling dielectric layer and a semiconductor channel can be subsequently formed.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: October 31, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Somesh Peri, Raghuveer S. Makala, Yanli Zhang
  • THREE-DIMENSIONAL MEMORY DEVICES HAVING A SHAPED EPITAXIAL CHANNEL PORTION AND METHOD OF MAKING THEREOF
    Publication number: 20170125437
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: Jayavel Pachamuthu, Sateesh Koka, Raghuveer S. Makala, Somesh Peri
  • METHOD OF MAKING SELF-ASSEMBLING FLOATING GATE ELECTRODES FOR A THREE-DIEMNSIONAL MEMORY DEVICE
    Publication number: 20170084623
    Abstract: Metal floating gate electrodes can be formed for a three-dimensional memory device by forming a memory opening having lateral recesses at levels of spacer material layers between insulating layers, depositing a continuous metal layer, and inducing diffusion and agglomeration of the metal into the lateral recesses to form discrete metal portions employing an anneal process. The metallic material can migrate and form the discrete metal portions due to surface tension, which operates to minimize the surface area of the metallic material. Optionally, two or more continuous metal layers can be employed to form discrete metal portions including at least two metals. Optionally, a selective metal deposition process can be performed to deposit additional metal portions including a different metallic material on the discrete metal portions. The metal floating gate electrodes can be formed without employing an etch process. A tunneling dielectric layer and a semiconductor channel can be subsequently formed.
    Type: Application
    Filed: February 29, 2016
    Publication date: March 23, 2017
    Inventors: Rahul SHARANGPANI, Somesh PERI, Raghuveer S. MAKALA, Yanli ZHANG
  • Three-dimensional memory devices having a shaped epitaxial channel portion and method of making thereof
    Patent number: 9754958
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: September 5, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jayavel Pachamuthu, Sateesh Koka, Raghuveer S. Makala, Somesh Peri
  • Cobalt-containing conductive layers for control gate electrodes in a memory structure
    Patent number: 9576966
    Abstract: An alternating stack of insulating layers and sacrificial material layers can be formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers from the backside trench selective to the insulating layers. A cobalt-containing material is deposited such that the cobalt-containing material continuously extends at least between a neighboring pair of cobalt-containing material portions in respective backside recesses. An anneal is performed at an elevated temperature to migrate vertically-extending portions of the cobalt-containing material into the backside recesses, thereby forming vertically separated cobalt-containing material portions confined within the backside recesses. Sidewalls of the insulating layers may be rounded or tapered to facilitate migration of the cobalt-containing material.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: February 21, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Somesh Peri, Raghuveer S. Makala, Sateesh Koka, Rahul Sharangpani
  • Three-dimensional memory device with amorphous barrier layer and method of making thereof
    Patent number: 10355139
    Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. An electrically conductive, amorphous barrier layer can be formed prior to formation of a metal fill material layer to provide a diffusion barrier that reduces fluorine diffusion between the metal fill material layer and memory films of memory stack structures. The electrically conductive, amorphous barrier layer can be an oxygen-containing titanium compound or a ternary transition metal nitride.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Keerti Shukla, Fei Zhou, Somesh Peri
  • Crystalinity-dependent aluminum oxide etching for self-aligned blocking dielectric in a memory structure
    Patent number: 9659955
    Abstract: A method of forming a device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, and forming an aluminum oxide layer on sidewall surfaces of the sacrificial material layers and on sidewall surfaces of the insulating layers around the memory opening. First aluminum oxide portions of the aluminum oxide layer are located on sidewall surfaces of the sacrificial material layers, and second aluminum oxide portions of the aluminum oxide layer are located on sidewalls of the insulating layers. The method also includes removing the second aluminum oxide portions at a greater etch rate than the first aluminum oxide portions employing a selective etch process, such that all or a predominant portion of each first aluminum oxide portion remains after removal of the second aluminum oxide portions.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: May 23, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Sateesh Koka, Raghuveer S. Makala, Somesh Peri, Senaka Kanakamedala
  • MEMORY DEVICE CONTAINING COBALT SILICIDE CONTROL GATE ELECTRODES AND METHOD OF MAKING THEREOF
    Publication number: 20170092733
    Abstract: An alternating stack of insulating layers and sacrificial material layers can be formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers from the backside trench selective to the insulating layers. A cobalt-semiconductor alloy portion is formed in each backside recess by reacting cobalt and a semiconductor material. Conductive material in the backside trench can be removed by an etch to electrically isolate cobalt-containing alloy portions located in different backside recesses. Electrically conductive layers including a respective cobalt-semiconductor alloy portion can be employed as word lines of a three-dimensional memory device.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 30, 2017
    Inventors: Raghuveer S. MAKALA, Sateesh KOKA, Zhenyu LU, Somesh PERI, Rahul SHARANGPANI
  • Cobalt-containing conductive layers for control gate electrodes in a memory structure
    Patent number: 9984963
    Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a backside blocking dielectric layer is formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A cobalt metal portion can be formed in each backside recess. Each backside recess can be filled with a portion of a backside blocking dielectric layer, a metallic barrier material portion, a cobalt metal portion, and a metallic material portion including a material other than cobalt.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: May 29, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Somesh Peri, Rahul Sharangpani, Raghuveer S. Makala, Senaka Kanakamedala, Keerti Shukla
  • COBALT-CONTAINING CONDUCTIVE LAYERS FOR CONTROL GATE ELECTRODES IN A MEMORY STRUCTURE
    Publication number: 20160351497
    Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a backside blocking dielectric layer is formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A cobalt metal portion can be formed in each backside recess. Each backside recess can be filled with a portion of a backside blocking dielectric layer, a metallic barrier material portion, a cobalt metal portion, and a metallic material portion including a material other than cobalt.
    Type: Application
    Filed: July 29, 2016
    Publication date: December 1, 2016
    Inventors: Somesh Peri, Rahul Sharangpani, Raghuveer S. Makala, Senaka Kanakamedala, Keerti Shukla
  • THREE-DIMENSIONAL MEMORY DEVICE WITH AMORPHOUS BARRIER LAYER AND METHOD OF MAKING THEREOF
    Publication number: 20170373197
    Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. An electrically conductive, amorphous barrier layer can be formed prior to formation of a metal fill material layer to provide a diffusion barrier that reduces fluorine diffusion between the metal fill material layer and memory films of memory stack structures. The electrically conductive, amorphous barrier layer can be an oxygen-containing titanium compound or a ternary transition metal nitride.
    Type: Application
    Filed: October 12, 2016
    Publication date: December 28, 2017
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Keerti Shukla, Fei Zhou, Somesh Peri
  • CRYSTALINITY-DEPENDENT ALUMINUM OXIDE ETCHING FOR SELF-ALIGNED BLOCKING DIELECTRIC IN A MEMORY STRUCTURE
    Publication number: 20170125436
    Abstract: A method of forming a device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, and forming an aluminum oxide layer on sidewall surfaces of the sacrificial material layers and on sidewall surfaces of the insulating layers around the memory opening. First aluminum oxide portions of the aluminum oxide layer are located on sidewall surfaces of the sacrificial material layers, and second aluminum oxide portions of the aluminum oxide layer are located on sidewalls of the insulating layers. The method also includes removing the second aluminum oxide portions at a greater etch rate than the first aluminum oxide portions employing a selective etch process, such that all or a predominant portion of each first aluminum oxide portion remains after removal of the second aluminum oxide portions.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 4, 2017
    Inventors: Rahul SHARANGPANI, Sateesh KOKA, Raghuveer S. MAKALA, Somesh PERI, Senaka KANAKAMEDALA
  • Memory device containing cobalt silicide control gate electrodes and method of making thereof
    Patent number: 9842907
    Abstract: An alternating stack of insulating layers and sacrificial material layers can be formed over a substrate. Memory stack structures and a backside trench are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers from the backside trench selective to the insulating layers. A cobalt-semiconductor alloy portion is formed in each backside recess by reacting cobalt and a semiconductor material. Conductive material in the backside trench can be removed by an etch to electrically isolate cobalt-containing alloy portions located in different backside recesses. Electrically conductive layers including a respective cobalt-semiconductor alloy portion can be employed as word lines of a three-dimensional memory device.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: December 12, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Sateesh Koka, Zhenyu Lu, Somesh Peri, Rahul Sharangpani
  • Robust nucleation layers for enhanced fluorine protection and stress reduction in 3D NAND word lines
    Patent number: 9793139
    Abstract: A silicon-containing nucleation layer can be employed to provide a self-aligned template for selective deposition of tungsten within backside recesses during formation of a three-dimensional memory device. The silicon-containing nucleation layer may remain as a silicon layer, converted into a tungsten silicide layer, or replaced with a tungsten nucleation layer. Tungsten deposition can proceed only on the surface of the silicon-containing nucleation layer or a layer derived therefrom in a subsequent tungsten deposition process.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 17, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Keerti Shukla, Raghuveer S. Makala, Somesh Peri, Yao-Sheng Lee
  • THREE-DIMENSIONAL MEMORY DEVICE WITH SEMICIRCULAR METAL-SEMICONDUCTOR ALLOY FLOATING GATE ELECTRODES AND METHODS OF MAKING THEREOF
    Publication number: 20180040623
    Abstract: Azimuthally-split metal-semiconductor alloy floating gate electrodes can be formed by providing an alternating stack of insulating layers and spacer material layers, forming a dielectric separator structure extending through the alternating stack, and forming memory openings that divides the dielectric separator structure into a plurality of dielectric separator structures. The spacer material layers are formed as, or are replaced with, electrically conductive layers, which are laterally recessed selective to the insulating layers and the plurality of dielectric separator structures to form a pair of lateral cavities at each level of the electrically conductive layers in each memory opening. After formation of a blocking dielectric layer, a pair of physically disjoined metal-semiconductor alloy portions are formed in each pair of lateral cavities as floating gate electrodes. A tunneling dielectric layer and a semiconductor channel layer is subsequently formed in each memory opening.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: Senaka Kanakamedala, Raghuveer S. Makala, Rahul Sharangpani, Somesh Peri, Yao-Sheng Lee
  • ROBUST NUCLEATION LAYERS FOR ENHANCED FLUORINE PROTECTION AND STRESS REDUCTION IN 3D NAND WORD LINES
    Publication number: 20170125538
    Abstract: A silicon-containing nucleation layer can be employed to provide a self-aligned template for selective deposition of tungsten within backside recesses during formation of a three-dimensional memory device. The silicon-containing nucleation layer may remain as a silicon layer, converted into a tungsten silicide layer, or replaced with a tungsten nucleation layer. Tungsten deposition can proceed only on the surface of the silicon-containing nucleation layer or a layer derived therefrom in a subsequent tungsten deposition process.
    Type: Application
    Filed: March 31, 2016
    Publication date: May 4, 2017
    Inventors: Rahul SHARANGPANI, Keerti SHUKLA, Raghuveer S. MAKALA, Somesh PERI, Yao-Sheng LEE
  • RIDGED WORD LINES FOR INCREASING CONTROL GATE LENGTHS IN A THREE-DIMENSIONAL MEMORY DEVICE
    Publication number: 20180040627
    Abstract: After formation of a memory opening through an alternating stack of insulating layers and sacrificial material layers, a blocking dielectric having a greater thickness at levels of the insulating layers than at levels of the sacrificial material layers is formed around, or within, the memory opening. A memory stack structure is formed within the memory opening. Backside recesses are formed by removing the sacrificial material layers and surface portions of the blocking dielectric to form backside recesses including vertically expanded end portions. Electrically conductive layers are formed within the backside recesses. Each of the electrically conductive layers is a control gate electrode which includes a uniform thickness portion and a ridged end portion having a greater vertical extent than the uniform thickness region. The ridged end portion laterally surrounds the memory stack structure and provides a longer gate length for the control gate electrodes for the memory stack structure.
    Type: Application
    Filed: August 8, 2016
    Publication date: February 8, 2018
    Inventors: Senaka Kanakamedala, Rahul Sharangpani, Raghuveer S. Makala, Somesh Peri, Yao-Sheng Lee
  • Ridged word lines for increasing control gate lengths in a three-dimensional memory device
    Patent number: 9893081
    Abstract: After formation of a memory opening through an alternating stack of insulating layers and sacrificial material layers, a blocking dielectric having a greater thickness at levels of the insulating layers than at levels of the sacrificial material layers is formed around, or within, the memory opening. A memory stack structure is formed within the memory opening. Backside recesses are formed by removing the sacrificial material layers and surface portions of the blocking dielectric to form backside recesses including vertically expanded end portions. Electrically conductive layers are formed within the backside recesses. Each of the electrically conductive layers is a control gate electrode which includes a uniform thickness portion and a ridged end portion having a greater vertical extent than the uniform thickness region. The ridged end portion laterally surrounds the memory stack structure and provides a longer gate length for the control gate electrodes for the memory stack structure.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 13, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Kanakamedala, Rahul Sharangpani, Raghuveer S. Makala, Somesh Peri, Yao-Sheng Lee
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