Search Patents
  • Analogues of N-acetylardeemin, method of preparation and uses thereof
    Patent number: 6147076
    Abstract: The present invention provides a compound having the structure: ##STR1## wherein R.sub.1 R.sub.6 and R.sub.7 are independently hydrogen, OH, NH.sub.2, SH, halogen, C.sub.1 -C.sub.9 linear or branched chain alkyl, alkylmercapto, alkylamino, dialkylamino, alkoxy, phenyl, etc.; wherein R.sub.0 and R.sub.2 are independently hydrogen, OH, linear or branched chain alkyl, --CR.sub.3 R.sub.3 --CH(O)CH.sub.2, --CR.sub.3 R.sub.3 --CH.sub.2 CH.sub.3, --CR.sub.3 R.sub.3 --CH.sub.2 CH.sub.2 OH, --CR.sub.3 R.sub.3 --CH(OH)R.sub.4 or --CR.sub.3 R.sub.3 --CH.dbd.CHR.sub.4 ; wherein R.sub.3 and R.sub.4 are independently hydrogen, halogen, C.sub.1 -C.sub.9 linear or branched chain alkyl, phenyl, etc.; wherein R.sub.5 is hydrogen, C.sub.1 -C.sub.9 linear or branched chain alkyl, phenyl, etc.; and wherein R.sub.8 is hydrogen, C.sub.1 -C.sub.9 linear or branched chain acyl, benzoyl, etc.; with the proviso that (a) when R.sub.2 is --CR.sub.3 R.sub.3 --CH(O)CH.sub.2, --CR.sub.3 R.sub.3 --CH.sub.2 CH.sub.3, --CR.sub.3 R.sub.3 --CH.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: November 14, 2000
    Assignees: Sloan-Kettering Institute for Cancer Research, The Trustees of Columbia University in the City of New York
    Inventors: Samuel J. Danishefsky, Kristopher Depew, Stephen P. Marsden, William Bornmann, Ting Chao Chou, Andrej Zatorski
  • SURFACE TREATMENT METHOD BY USING THE NH3 PLASMA TREATMENT TO MODIFY THE SENSING THIN-FILM
    Publication number: 20120322167
    Abstract: The NH3 plasma treatment by remote plasma is firstly proposed to replace the covalent bonding process during surface modification procedure that for amine bond generation.
    Type: Application
    Filed: May 8, 2012
    Publication date: December 20, 2012
    Applicant: Chang Gung University
    Inventors: Chao-Sung LAI, Jau-Song Yu, Yu-Sun Chang, Po-Lung Yang, Tseng-Fu Lu, Yi-Ting Lin, Wen-Yu Chuang, Ting-Chun Yu, I-Shun Wang, Jyh-Ping Chen, Chou Chien
  • Surface treatment method by using the NHplasma treatment to modify the sensing thin-film
    Patent number: 8741679
    Abstract: The NH3 plasma treatment by remote plasma is firstly proposed to replace the covalent bonding process during surface modification procedure that for amine bond generation.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: June 3, 2014
    Assignee: Chang Gung University
    Inventors: Chao-Sung Lai, Jau-Song Yu, Yu-Sun Chang, Po-Lung Yang, Tseng-Fu Lu, Yi-Ting Lin, Wen-Yu Chuang, Ting-Chun Yu, I-Shun Wang, Jyh-Ping Chen, Chou Chien
  • SEMICONDUCTOR DEVICE PRE-CLEANING
    Publication number: 20230386822
    Abstract: A pre-cleaning technique described herein may be used to remove native oxides and/or other contaminants from a semiconductor device in a manner in which the likelihood of chopping, clipping, and/or sidewall spacer thickness reduction is reduced. As described herein, a protection layer is formed on a capping layer over a gate structure of a transistor. A pre-cleaning operation is then performed to remove native oxides from the top surface of a source/drain region of the transistor. In the pre-cleaning operation, the protection layer is consumed instead of the material of the capping layer. In this way, the use of the protection layer reduces the likelihood of removal of material from the capping layer and/or reduces the amount of material that is removed from the capping layer during the pre-cleaning operation.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Inventors: Yi-Hsiang CHAO, Chih-Sheng CHOU, Shu-Ting YANG, Ting-Wei WENG, Peng-Hao HSU, Chun-Hsien HUANG, Hung-Hsu CHEN, Hung-Chang HSU, Chih-Wei CHANG, Ming-Hsing TSAI
  • PHOTOGRAPHING APPARATUS AND CONTROL METHOD THEREOF
    Publication number: 20110075012
    Abstract: A method for controlling a photographing apparatus is provided. The photographing apparatus includes a touch screen. In the method, it is first detected whether a user keeps touching a focus point on the touch screen for a specific duration. If the detected result is YES, the photographing apparatus is controlled to perform an automatic focusing procedure corresponding to the focus point and then an automatic photographing procedure.
    Type: Application
    Filed: November 13, 2008
    Publication date: March 31, 2011
    Applicant: BENQ CORPORATION
    Inventors: Wen-Kang Chen, Chia-Chen Chao, Shuo-Yen Ho, Yi-Ting Chou
  • METHOD AND APPARATUS FOR ORCHESTRATING RESOURCES IN MULTI-ACCESS EDGE COMPUTING (MEC) NETWORK
    Publication number: 20210136007
    Abstract: A method for orchestrating resources in a multi-access edge computing (MEC) network is applied in and by an apparatus. The MEC network comprises at least one control node, substrate nodes and substrate links managed by the at least one control node. The apparatus receives a virtual network request and calculates whether a proper virtual network embedding solution for the virtual network request exists. If so, the apparatus hands the solution over to the at least one control node for implementation.
    Type: Application
    Filed: June 18, 2020
    Publication date: May 6, 2021
    Inventors: HUNG-YU WEI, CHUN-TING CHOU, KUO-LIANG CHANG CHIEN, YAO CHIANG, YU-HSIANG CHAO
  • Method and apparatus for orchestrating resources in multi-access edge computing (MEC) network
    Patent number: 10986036
    Abstract: A method for orchestrating resources in a multi-access edge computing (MEC) network is applied in and by an apparatus. The MEC network comprises at least one control node, substrate nodes and substrate links managed by the at least one control node. The apparatus receives a virtual network request and calculates whether a proper virtual network embedding solution for the virtual network request exists. If so, the apparatus hands the solution over to the at least one control node for implementation.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: April 20, 2021
    Assignee: HON LIN TECHNOLOGY CO., LTD.
    Inventors: Hung-Yu Wei, Chun-Ting Chou, Kuo-Liang Chang Chien, Yao Chiang, Yu-Hsiang Chao
  • Raised fuse structure for laser repair
    Patent number: 5729042
    Abstract: A novel raised polycide fusible link structure is described. This structure enables a highly reliable laser-cutting process to be used in which the fuse can be easily and totally severed over a wide range of laser energy levels. The primary feature of the structure is that the fusible link is located on a pedestal that raises it above the surface of the main body of the integrated circuit, thereby providing a measure of thermal isolation for the fuse when it is irradiated by the laser. An efficient process for manufacturing the structure is also described.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: March 17, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yung-Song Lou, Ching-Cherng Rou, Ting Chou, Chao-Ming Koh, Shin-Chi Lee, Chuen-Nan Chen
  • Raised fuse structure for laser repair
    Patent number: 5910678
    Abstract: A novel raised polycide fusible link structure is described. This structure enables a highly reliable laser-cutting process to be used in which the fuse can be easily and totally severed over a wide range of laser energy levels. The primary feature of the structure is that the fusible link is located on a pedestal that raises it above the surface of the main body of the integrated circuit, thereby providing a measure of thermal isolation for the fuse when it is irradiated by the laser. An efficient process for manufacturing the structure is also described.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: June 8, 1999
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yung-Song Lou, Ching-Cherng Rou, Ting Chou, Chao-Ming Koh, Shin-Chi Lee, Chuen-Nan Chen
  • CONTAINER DATA CENTER
    Publication number: 20170105318
    Abstract: A container data center includes a container, two server cabinet groups, and a power supply equipment group. The container includes an interior. The two server cabinet groups are respectively arranged at two opposite ends of the interior of the container. The power supply equipment group is arranged in the container between the two server cabinet groups.
    Type: Application
    Filed: November 16, 2015
    Publication date: April 13, 2017
    Inventors: TZE-CHERN MAO, CHIH-HUNG CHANG, YEN-CHUN FU, YAO-TING CHANG, CHAO-KE WEI, HUNG-CHOU CHAN
  • Backside Power Rail Structure and Methods of Forming Same
    Publication number: 20220181259
    Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang
  • BACKSIDE POWER RAIL STRUCTURE AND METHODS OF FORMING SAME
    Publication number: 20240063125
    Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang
  • FINFET SEMICONDUCTOR DEVICE HAVING FINS WITH STRONGER STRUCTURAL STRENGTH
    Publication number: 20160307894
    Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.
    Type: Application
    Filed: April 14, 2015
    Publication date: October 20, 2016
    Inventors: Chao-Hsin CHIEN, Chen-Han CHOU, Cheng-Ting CHUNG, Samuel C. PAN
  • Backside Power Rail Structure and Methods of Forming Same
    Publication number: 20210134721
    Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
    Type: Application
    Filed: July 27, 2020
    Publication date: May 6, 2021
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230067664
    Abstract: A package structure includes a circuit substrate, a package element and a molding layer. The package element is disposed on the circuit substrate and is electrically connected with the circuit substrate. The molding layer is disposed over the circuit substrate and covers at least a top surface of the circuit substrate. The molding layer includes a first portion wrapping around sidewalls of the package element and having a first thickness, and a second portion surrounding the first portion and connected with the first portion. The first thickness of the first portion is larger than a second thickness of the second portion. A top surface of the first portion of the molding layer is higher than a top surface of the package element.
    Type: Application
    Filed: July 15, 2022
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Wei Li, Tzu-Ting Chou, Chun-Yen Lan, Yu-Wei Lin, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • FINFET SEMICONDUCTOR DEVICE HAVING FINS WITH STRONGER STRUCTURAL STRENGTH
    Publication number: 20170125415
    Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.
    Type: Application
    Filed: October 13, 2016
    Publication date: May 4, 2017
    Inventors: Chao-Hsin CHIEN, Chen-Han CHOU, Cheng-Ting CHUNG, Samuel C. PAN
  • Backside power rail structure and methods of forming same
    Patent number: 11842965
    Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang
  • INTEGRATION OF MULTIPLE FIN STUCTURES ON A SINGLE SUBSTRATE
    Publication number: 20210296312
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) including a first fin structure and a second fin structure vertically extending from a semiconductor substrate, respectively. The first fin structure laterally extends along a first direction and has a first width. The second fin structure laterally extends along the first direction and has a second width that is less than the first width. A first plurality of nanostructures directly overlies the first fin structure and is vertically spaced from the first fin structure by a non-zero distance. A gate electrode continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The gate electrode directly overlies the first and second fin structures, and wraps around the nanostructures.
    Type: Application
    Filed: March 19, 2020
    Publication date: September 23, 2021
    Inventors: Chih-Chao Chou, Chih-Hao Wang, Shi Ning Ju, Kuo-Cheng Chiang, Wen-Ting Lan
  • Backside power rail structure and methods of forming same
    Patent number: 11264327
    Abstract: Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230062468
    Abstract: A package structure including a substrate, a first semiconductor element disposed on and electrically connected with the substrate, a second semiconductor element disposed on and electrically connected with the substrate and a molding layer disposed over the substrate and covering at least a top surface of the substrate. The second semiconductor element and the first semiconductor element perform different functions. The molding layer encapsulates the second semiconductor element and wraps around sidewalls of the first semiconductor element. A top surface of the molding layer is higher than a top surface of the first semiconductor element. The molding layer has an opening extending from the top surface of the molding layer to the top surface of the first semiconductor element, so that the top surface of the first semiconductor element is exposed.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Hsiang Chiu, Chia-Min Lin, Tzu-Ting Chou, Sheng-Feng Weng, Chao-wei Li, Chih-Wei Lin, Ching-Hua Hsieh
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