Search Patents
  • PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230062468
    Abstract: A package structure including a substrate, a first semiconductor element disposed on and electrically connected with the substrate, a second semiconductor element disposed on and electrically connected with the substrate and a molding layer disposed over the substrate and covering at least a top surface of the substrate. The second semiconductor element and the first semiconductor element perform different functions. The molding layer encapsulates the second semiconductor element and wraps around sidewalls of the first semiconductor element. A top surface of the molding layer is higher than a top surface of the first semiconductor element. The molding layer has an opening extending from the top surface of the molding layer to the top surface of the first semiconductor element, so that the top surface of the first semiconductor element is exposed.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Hsiang Chiu, Chia-Min Lin, Tzu-Ting Chou, Sheng-Feng Weng, Chao-wei Li, Chih-Wei Lin, Ching-Hua Hsieh
  • SEMICONDUCTOR DEVICE WITH BACKSIDE SELF-ALIGNED POWER RAIL AND METHODS OF FORMING THE SAME
    Publication number: 20220359699
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 10, 2022
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Integration of multiple fin structures on a single substrate
    Patent number: 11342325
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) including a first fin structure and a second fin structure vertically extending from a semiconductor substrate, respectively. The first fin structure laterally extends along a first direction and has a first width. The second fin structure laterally extends along the first direction and has a second width that is less than the first width. A first plurality of nanostructures directly overlies the first fin structure and is vertically spaced from the first fin structure by a non-zero distance. A gate electrode continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The gate electrode directly overlies the first and second fin structures, and wraps around the nanostructures.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chao Chou, Chih-Hao Wang, Shi Ning Ju, Kuo-Cheng Chiang, Wen-Ting Lan
  • INTEGRATION OF MULTIPLE FIN STUCTURES ON A SINGLE SUBSTRATE
    Publication number: 20220285343
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a stack of semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers over a semiconductor substrate. A first stack of masking layers is formed over the stack of semiconductor layers with a first width and a second stack of masking layers is formed laterally offset from the stack of semiconductor layers with a second width less than the first width. A patterning process is performed on the semiconductor substrate and the stack of semiconductor layers, thereby defining a first fin structure laterally adjacent to a second fin structure. The first fin structure has the first width and the second fin structure has the second width. The stack of semiconductor layers directly overlies the first fin structure and has the first width.
    Type: Application
    Filed: May 19, 2022
    Publication date: September 8, 2022
    Inventors: Chih-Chao Chou, Chih-Hao Wang, Shi Ning Ju, Kuo-Cheng Chiang, Wen-Ting Lan
  • Semiconductor Device with Backside Self-Aligned Power Rail and Methods of Forming the Same
    Publication number: 20220293759
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • INTEGRATED CIRCUITS WITH BACKSIDE POWER RAILS
    Publication number: 20220344254
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Application
    Filed: July 8, 2022
    Publication date: October 27, 2022
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Semiconductor device with backside self-aligned power rail and methods of forming the same
    Patent number: 11444170
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Integrated circuits with backside power rails
    Patent number: 11742280
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • FinFET semiconductor device having fins with stronger structural strength
    Patent number: 9859276
    Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: January 2, 2018
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Chiao-Tung University
    Inventors: Chao-Hsin Chien, Chen-Han Chou, Cheng-Ting Chung, Samuel C. Pan
  • COOLING SYSTEM FOR DATA CENTER
    Publication number: 20170112023
    Abstract: A cooling system for data center includes a server cabinet, a electronic equipment and a cooling module. The server cabinet includes a number of first check valves and second check valves. The cooling module includes a number of first cooling fans and heat-exchange equipments. The cooling system for data center can turn on or turn off the first cooling fans or the heat-exchange equipments to cool the electronic equipment if needed.
    Type: Application
    Filed: December 18, 2015
    Publication date: April 20, 2017
    Inventors: TZE-CHERN MAO, CHIH-HUNG CHANG, YEN-CHUN FU, YAO-TING CHANG, CHAO-KE WEI, HUNG-CHOU CHAN
  • Integrated circuits with backside power rails
    Patent number: 11387181
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Method for Estimating Binding Kinetic Rate Constants by Using Fiber Optics Particle Plasmon Resonance (FOPPR) Sensor
    Publication number: 20130122608
    Abstract: A method for estimating binding kinetic rate constants by using a fiber optic particle plasmon resonance (FOPPR) sensor mainly employs the steps of: providing a FOPPR sensor instrument system, obtaining optical signal intensities at an initial time and steady state signal intensities of first and second regions in an intensity versus time graph separately, substituting the measured signal intensity values into a formula derived by using a pseudo-first order rate equation model. According to this method, no fluorophore labeling is required. In addition, this method measures a temporal signal intensity evolution under static conditions as the samples are quickly loaded. As a result, unlike the conventional device where the sample is continuously infused, the method is able to measure binding and decomposition rate constants whose upper limit is not limited by a sample flow rate.
    Type: Application
    Filed: May 14, 2012
    Publication date: May 16, 2013
    Applicant: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: SHAU-CHUN WANG, LAI-KWAN CHAU, TING-CHOU CHANG, CHAO-CHING WU
  • FinFET semiconductor device having fins with stronger structural strength
    Patent number: 9496259
    Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: November 15, 2016
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO-TUNG UNIVERSITY
    Inventors: Chao-Hsin Chien, Chen-Han Chou, Cheng-Ting Chung, Samuel C. Pan
  • Selective formation of titanium silicide and titanium nitride by hydrogen gas control
    Patent number: 11972951
    Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Kao-Feng Lin, Min-Hsiu Hung, Yi-Hsiang Chao, Huang-Yi Huang, Yu-Ting Lin
  • INTEGRATED CIRCUITS WITH BACKSIDE POWER RAILS
    Publication number: 20230369196
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Integrated Circuits with Backside Power Rails
    Publication number: 20200381352
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Inventors: Chih-Chao Chou, Kuo-Cheng Ching, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • METHOD FOR OBTAINING BINDING KINETIC RATE CONSTANTS USING FIBER OPTIC PARTICLE PLASMON RESONANCE (FOPPR) SENSOR
    Publication number: 20140051188
    Abstract: A method for obtaining the binding kinetic rate constants using fiber optic particle plasmon resonance (FOPPR) sensor, suitable for a test solution with two or more concentrations, which employs the following major steps: providing one FOPPR sensor instrument system, obtaining optical time-resolved signal intensities starting at the initial time to the steady state of the two or more regions, substituting the measured signal intensity values into the formula which is derived by using the pseudo-first order rate equation model. In addition, this method measures the temporal signal intensity evolution under static conditions as the samples are quickly loaded. As a result, unlike the conventional device where the sample is continuously infused, the method is able to measure the association and dissociation rate constants of which the upper bounds are not limited by the sample flow rate.
    Type: Application
    Filed: October 25, 2013
    Publication date: February 20, 2014
    Applicant: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: SHAU-CHUN WANG, LAI-KWAN CHAU, TING-CHOU CHANG, CHAO-CHING WU
  • Integrated Circuits with Backside Power Rails
    Publication number: 20210057325
    Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Inventors: Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan, Chih-Hao Wang
  • Method for obtaining binding kinetic rate constants using fiber optic particle plasmon resonance (FOPPR) sensor
    Patent number: 9506861
    Abstract: A method for obtaining the binding kinetic rate constants using fiber optic particle plasmon resonance (FOPPR) sensor, suitable for a test solution with two or more concentrations, which employs the following major steps: providing one FOPPR sensor instrument system, obtaining optical time-resolved signal intensities starting at the initial time to the steady state of the two or more regions, substituting the measured signal intensity values into the formula which is derived by using the pseudo-first order rate equation model. In addition, this method measures the temporal signal intensity evolution under static conditions as the samples are quickly loaded. As a result, unlike the conventional device where the sample is continuously infused, the method is able to measure the association and dissociation rate constants of which the upper bounds are not limited by the sample flow rate.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: November 29, 2016
    Assignee: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: Shau-Chun Wang, Lai-Kwan Chau, Ting-Chou Chang, Chao-Ching Wu
  • LIFEPO4 Precursor for manufacturing electrode material of Li-ion battery and method for manufacturing the same
    Publication number: 20190386306
    Abstract: An LiFePO4 precursor for manufacturing an electrode material of an Li-ion battery and a method for manufacturing the same are disclosed. The LiFePO4 precursor of the present disclosure can be represented by the following formula (I): LiFe(1-a)MaPO4??(I) wherein M and a are defined in the specification, the LiFePO4 precursor does not have an olivine structure, and the LiFePO4 precursor is powders constituted by plural flakes.
    Type: Application
    Filed: August 28, 2019
    Publication date: December 19, 2019
    Inventors: Lih-Hsin Chou, Li-Wen Hu, Chun-Yu Pan, Shao-Ting Hung, Kuei-Chao Wu
Narrow Results

Filter by US Classification