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  • Error correctable data transmission method
    Patent number: 4413340
    Abstract: An error correcting encoding and decoding system for transmission and reception of digital data is arranged for high error-correcting ability of both burst errors and random errors. In encoding apparatus a digital signal is processed as a plurality of word sequences. The words are interleaved into a different arranging order and are subjected to different relative amounts of delay. Then, first check words are generated to satisfy a parity detection matrix, such as a Reed-Solomon code matrix. After this, the resulting data words and first check words are again interleaved and are provided with respective different amounts of delay. Then, second check words are generated to satisfy a similar matrix. Finally, the first and second check words and the data words are interleaved prior to transmission.
    Type: Grant
    Filed: November 12, 1981
    Date of Patent: November 1, 1983
    Assignee: Sony Corporation
    Inventors: Kentaro Odaka, Yoichiro Sako, Ikuo Iwamoto, Toshitada Doi, Lodewijk B. Vries
  • Method and apparatus for encoding digital with two error correcting codes
    Patent number: 4398292
    Abstract: Successive data words are distributed to a plurality of respective channels to form successive data blocks, each data block being comprised of the data words in the plural channels. A first error correcting code is generated as a function of the words included in the data block, this first error correcting code being adapted for use in correcting at least one word which may be erroneous in the data block, as when the data block subsequently is received or reproduced. The data words included in the data block are selectively delayed, by different respective time delays, to form a time-interleaved data block comprised of time-interleaved data words. A second error correcting code is generated as a function of the words included in the time-interleaved data block, this second error correcting code being adapted for use in correcting at least one word which may be erroneous in the time-interleaved data block, as when the time-interleaved data block subsequently is received or reproduced.
    Type: Grant
    Filed: February 23, 1981
    Date of Patent: August 9, 1983
    Assignee: Sony Corporation
    Inventors: Toshitada Doi, Kentarou Odaka
  • Encoding for error correction of recorded digital signals
    Patent number: 4206440
    Abstract: Digital signals consisting of sets of simultaneous bits have an error-correcting signal encoded into them by adding an error-correcting bit to each set. The sets thus enlarged are referred to as digital words. The digital signals are then converted from simultaneous, or parallel, form to serial, or sequential, form and the digital words from a block of several digital signals at a time are interleaved in such a way that corresponding words from each of the digital signals in the same block are placed in immediate sequence. Prior to adding the error-correcting bits error-detecting bits can be added to the original bits in intersecting sets can that intersect the first-mentioned sets in row by column relationship, and parity bits can also be formed simultaneously with the formation of the error-correcting bits as extensions of the intersecting sets.
    Type: Grant
    Filed: December 15, 1977
    Date of Patent: June 3, 1980
    Assignee: Sony Corporation
    Inventors: Toshitada Doi, Shinichi Kazami
  • Method and apparatus for communicating digital information words by error-correction encoding
    Patent number: 4393502
    Abstract: A method and appratus are provided for communicating a sequence of digital information words. The information words are separated into a sequence of odd information words and a sequence of even information words. The separated odd and even information words are time-displaced from each other by a predetermined amount. The odd information words are encoded in an error-correcting code, and the even information words are separately encoded in a similar error-correcting code. The encoded time-displaced odd and even information words are combined into a transmission block, and this transmission block is transmitted or recorded. In one embodiment, the information words are encoded by generating an error-correcting word in response to the odd information words and by generating an error-correcting word in response to the even information words. The respective error-correcting words are interleaved with the odd and even information words.
    Type: Grant
    Filed: October 9, 1980
    Date of Patent: July 12, 1983
    Inventors: Masato Tanaka, Shunsuke Furukawa, Ikuo Iwamoto, Toshitada Doi
  • Method and system for transmitting and receiving blocks of encoded data words to minimize error distortion in the recovery of said data words
    Patent number: 4188616
    Abstract: A plurality l of data blocks, each comprised of at least two data words and a parity word associated bit for bit with the data words, together with an error correcting code word associated with each data and parity word, are transmitted in interleaved relation. L data words and associated error correcting code words followed by l parity words and associated error correcting code words and followed by l data words and associated error correcting code words, all transmitted in seriatim, are received and stored, and each error correcting word is decoded to ascertain the presence of an error in each received data or parity word.
    Type: Grant
    Filed: May 15, 1978
    Date of Patent: February 12, 1980
    Assignee: Sony Corporation
    Inventors: Shin-Ichi Kazami, Toshitada Doi
  • Digital signal transmission method
    Patent number: 4215335
    Abstract: Groups of primary multi-bit digital signals arranged in digital words are spaced apart in sequence and are interleaved with related groups of secondary multi-bit digital signals, each of which is derived from, and encodes substantially the same information as, one of the primary signals. To minimize errors in processing signals, either the primary signals are delayed relative to the secondary signals, or vice versa, before they are interleaved. Cyclic redundancy check code signals are derived for each group of primary signals and each group of secondary signals and are interleaved in sequence with the primary and secondary signals. At a further stage in processing the signals, the checked code signals are analized and the related pairs of primary and secondary signals, which have been brought back into coincidence, are checked to determine whether one or both of the primary and the secondary signals of each related pair has been processed without error.
    Type: Grant
    Filed: December 28, 1977
    Date of Patent: July 29, 1980
    Assignee: Sony Corporation
    Inventors: Toshitada Doi, Takashi Ito
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