Search Patents
  • Method, system, and product for verifying voltage drop across an entire integrated circuit package
    Publication number: 20050138584
    Abstract: A method, system, and product are disclosed for determining a voltage drop across an entire integrated circuit package. A geometric description of the entire integrated circuit package is determined. The description is subdivided into non-uniform areas. A resistance of each one of the non-uniform areas is determined. A resistive netlist of the entire integrated circuit package is then determined by combining the resistance of each one of the non-uniform areas. The package is then simulated utilizing the netlist to determine the voltage drop across the entire integrated circuit package.
    Type: Application
    Filed: December 17, 2003
    Publication date: June 23, 2005
    Applicant: International Business Machines Corporation
    Inventors: Michael Beattie, Anirudh Devgan, Byron Krauter, Hui Zheng
  • Lithographically optimized placement tool
    Patent number: 7434188
    Abstract: A system and a method are disclosed for integrating the results of lithographic simulation into the physical synthesis process. The effects of lithographic variation are considered when selecting a cell from among a group of cells having equivalent function. Circuit design elements are placed and routed with consideration of the effects of lithographic variation on robustness, timing performance, and leakage current. Cells may be simulated under a variety of conditions and environments and the simulation results stored in a library for efficient lithographically optimized placements.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: October 7, 2008
    Assignee: Magma Design Automation, Inc.
    Inventors: Anirudh Devgan, Roderick Metcalfe, Vivek Raghavan, Alfred Wong
  • LITHOGRAPHY AWARE LEAKAGE ANALYSIS
    Publication number: 20080052646
    Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
    Type: Application
    Filed: July 20, 2007
    Publication date: February 28, 2008
    Applicant: Magma Design Automation, Inc.
    Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
  • LITHOGRAPHY AWARE LEAKAGE ANALYSIS
    Publication number: 20140181762
    Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
    Type: Application
    Filed: October 29, 2013
    Publication date: June 26, 2014
    Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
  • Method of and system for buffer insertion, layer assignment, and wire sizing using wire codes
    Patent number: 7036104
    Abstract: A method of and system for optimizing a tree to meet timing constraints inserts buffers at selected ones of the internal nodes of a tree to form a plurality of subtrees. The method sizes the wires of the subtrees according to a wire code for each subtree, wherein each wire of a subtree has the same wire code. The buffers are inserted and the wires are sized such that slack along the path from a single source node to each sink node of the tree is equal to or greater than zero.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: April 25, 2006
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Steven Thomas Quay, Anirudh Devgan
  • LITHOGRAPHY AWARE TIMING ANALYSIS
    Publication number: 20080052653
    Abstract: A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
    Type: Application
    Filed: July 20, 2007
    Publication date: February 28, 2008
    Applicant: Magma Design Automation, Inc.
    Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
  • Method, system, and product for verifying voltage drop across an entire integrated circuit package
    Patent number: 7134103
    Abstract: A method, system, and product are disclosed for determining a voltage drop across an entire integrated circuit package. A geometric description of the entire integrated circuit package is determined. The description is subdivided into non-uniform areas. A resistance of each one of the non-uniform areas is determined. A resistive netlist of the entire integrated circuit package is then determined by combining the resistance of each one of the non-uniform areas. The package is then simulated utilizing the netlist to determine the voltage drop across the entire integrated circuit package.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: November 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Michael Werner Beattie, Anirudh Devgan, Byron Lee Krauter, Hui Zheng
  • Lithography aware leakage analysis
    Patent number: 9576098
    Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: February 21, 2017
    Assignee: Synopsys, Inc.
    Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
  • Lithography aware leakage analysis
    Patent number: 8572523
    Abstract: A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: October 29, 2013
    Assignee: Synopsys, Inc.
    Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
  • Lithography aware timing analysis
    Patent number: 8473876
    Abstract: A method for performing timing analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined. Delay information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: June 25, 2013
    Assignee: Synopsys, Inc.
    Inventors: Emre Tuncer, Hui Zheng, Vivek Raghavan, Anirudh Devgan, Amir Ajami, Alessandra Nardi, Tao Lin, Pramod Thazhathethil, Alfred Wong
  • METHOD FOR EVALUATING LEAKAGE EFFECTS ON STATIC MEMORY CELL ACCESS TIME
    Publication number: 20070153599
    Abstract: A method for evaluating leakage effects on static memory cell access time provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the states of other static memory cells connected to the same bitline as a static memory cell under test, the effect of leakage on the access time of the cell can be observed. The leakage effects can further be observed while varying the internal symmetry of the memory cell, operating the cell and observing changes in performance caused by the asymmetric operation. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage.
    Type: Application
    Filed: March 14, 2007
    Publication date: July 5, 2007
    Inventors: Rajiv Joshi, Qiuyi Ye, Anirudh Devgan
  • Two moment RC delay metric for performance optimization
    Patent number: 6434729
    Abstract: An efficient method for optimizing RC circuit design to reduce delay. The method comprises: calculating a first moment and a second moment of impulse response for an RC circuit; (2) computing a delay value for each node of the RC circuit utilizing the first and second moments by multiplying the natural logarithm of 2 with a division of the squared power of the first impulse moment by the square root of the second impulse moment; and (3) analyzing each node to determine if the delay at that node is at a desired optimization condition for optimizing the circuit response.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: August 13, 2002
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Anirudh Devgan, Chandramouli V. Kashyap
  • Bitline variable methods and circuits for evaluating static memory cell dynamic stability
    Publication number: 20070058448
    Abstract: Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the changes in the bitline voltage, the dynamic stability of the SRAM cell can be studied over designs and operating environments. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. In addition, cell power supply voltages can be split and set to different levels in order to study the effect of cell asymmetry in combination with bitline pre-charge voltage differences.
    Type: Application
    Filed: September 13, 2005
    Publication date: March 15, 2007
    Inventors: Rajiv Joshi, Qiuyi Ye, Anirudh Devgan
  • Efficient electromagnetic modeling of irregular metal planes
    Publication number: 20060282798
    Abstract: A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
    Type: Application
    Filed: June 14, 2005
    Publication date: December 14, 2006
    Inventors: Michael Beattie, Anirudh Devgan, Byron Krauter, Hui Zheng
  • EFFICIENT ELECTROMAGNETIC MODELING OF IRREGULAR METAL PLANES
    Publication number: 20070300191
    Abstract: A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.
    Type: Application
    Filed: September 3, 2007
    Publication date: December 27, 2007
    Inventors: Michael Beattie, Anirudh Devgan, Byron Krauter, Hui Zheng
  • Method and apparatus for realizable interconnect reduction for on-chip RC circuits
    Patent number: 6308304
    Abstract: Realizable interconnect reduction techniques for on-chip RC interconnects are disclosed by first partitioning the original circuit into sets of two-port circuits to maintain the spatial sparsity of the reduced model. Each original two-port circuit is matched to a reduced RC circuit having a specific configuration. The moments of the original two-port circuits are calculated. Closed form expression values of the reduced circuit elements are then calculated from the moments of the original circuits. The closed form expressions for calculating the values of the elements in the reduced circuit use a reduced number of independent variables associated with the elements, thus simplifying the calculations. An efficient linear time moment computation technique is used for computing the moments for the two-port circuits.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: October 23, 2001
    Assignee: International Business Machines Corporation
    Inventors: Anirudh Devgan, Peter Redmond O'Brien
  • Method, apparatus, and program for block-based static timing analysis with uncertainty
    Publication number: 20040243954
    Abstract: A block-based statistical timing analysis technique is provided in which the delay and arrival times in the circuit are modeled as random variables. The arrival times are modeled as Cumulative Probability Distribution Functions (CDFs) and the gate delays are modeled as Probability Density Functions (PDFs). This leads to efficient expressions for both max and addition operations, the two key functions in both regular and statistical timing analysis. Although the proposed approach can handle any form of the CDF, the CDFs may also be modeled as piecewise linear for computational efficiency. The dependency caused by reconvergent fanout is addressed, which is a necessary first step in a statistical STA framework. Reconvergent fanouts are efficiently handled by a common mode removal approach using statistical “subtraction.
    Type: Application
    Filed: May 29, 2003
    Publication date: December 2, 2004
    Applicant: International Business Machines Corporation
    Inventors: Anirudh Devgan, Chandramouli V. Kashyap
  • Method, system, and product for determining loop inductance of an entire integrated circuit package
    Publication number: 20040176939
    Abstract: A method, system, and product are disclosed for determining an inductance of an entire integrated circuit package taken as a whole. A model is generated of the entire integrated circuit package which has a first port, a second port, and a third port. The first port of the model is coupled in parallel to an energy source and a resistor having a known resistance. The second port of the model is shorted. And, the third port of the model is opened. The package is simulated by exciting the first port utilizing the energy source and measuring a voltage at the first port in order to produce a waveform. A time constant is determined utilizing the waveform. The inductance of the entire integrated circuit package is then determined from the first port with respect to the second port using the known resistance and the time constant.
    Type: Application
    Filed: March 6, 2003
    Publication date: September 9, 2004
    Applicant: International Business Machines Corporation
    Inventors: Michael Werner Beattie, Anirudh Devgan, Byron Lee Krauter
  • Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation
    Patent number: 6347393
    Abstract: An optimal buffer is chosen for insertion at a node by calculating a &pgr;-model of a downstream circuit to a child node where the &pgr;-model contains at least a capacitance value. The gate delay is computed at the node using an effective capacitance derived from the &pgr;-model and buffer characteristics of a particular buffer. The interconnect delay is then computed from sets of moments associated with each gate downstream from the node via a bottom-up incremental technique. Slack is computed using the gate delay for the child node and the interconnect delay for the child node and then the computed slack is compared to the slack of other buffers at the node. The node may be a sink or have one or two children.
    Type: Grant
    Filed: May 24, 1999
    Date of Patent: February 12, 2002
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Anirudh Devgan, Stephen Thomas Quay
  • Method, apparatus, and program for block-based static timing analysis with uncertainty
    Patent number: 7000205
    Abstract: A block-based statistical timing analysis technique is provided in which the delay and arrival times in the circuit are modeled as random variables. The arrival times are modeled as Cumulative Probability Distribution Functions (CDFs) and the gate delays are modeled as Probability Density Functions (PDFs). This leads to efficient expressions for both max and addition operations, the two key functions in both regular and statistical timing analysis. Although the proposed approach can handle any form of the CDF, the CDFs may also be modeled as piecewise linear for computational efficiency. The dependency caused by reconvergent fanout is addressed, which is a necessary first step in a statistical STA framework. Reconvergent fanouts are efficiently handled by a common mode removal approach using statistical “subtraction.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: February 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Anirudh Devgan, Chandramouli V. Kashyap
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