Search Patents
  • Technology for web site crawling, including action sequences for selecting non-hypertext-link parameters
    Publication number: 20130041882
    Abstract: A web site page has a reference for providing an address for a next page. The web site is crawled by the crawler program, which parses the reference from one of the web pages and sends the reference to an applet running in the browser. The address for the next page is determined by the browser responsive to the reference and is sent to the crawler.
    Type: Application
    Filed: August 30, 2012
    Publication date: February 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elizabeth Adleberg Brodsky, Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony
  • TOLERATING SOFT ERRORS BY SELECTIVE DUPLICATION
    Publication number: 20110296228
    Abstract: A method, system, and computer usable program product for tolerating soft errors by selective duplication are provided in the illustrative embodiments. An application executing in a data processing system, selects an instruction that has to be protected from soft errors. The instruction is marked for duplication such that the instruction is duplicated during execution of the instruction. The marked instruction is sent for execution to a hardware front end.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventors: ELMOOTAZBELLAH NABIL ELNOZAHY, Mark William Stephenson
  • Tolerating soft errors by selective duplication
    Patent number: 8271831
    Abstract: A method, system, and computer usable program product for tolerating soft errors by selective duplication are provided in the illustrative embodiments. An application executing in a data processing system, selects an instruction that has to be protected from soft errors. The instruction is marked for duplication such that the instruction is duplicated during execution of the instruction. The marked instruction is sent for execution to a hardware front end.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah Nabil Elnozahy, Mark William Stephenson
  • Mechanisms for Reducing DRAM Power Consumption
    Publication number: 20110296097
    Abstract: Mechanisms are provided for inhibiting precharging of memory cells of a dynamic random access memory (DRAM) structure. The mechanisms receive a command for accessing memory cells of the DRAM structure. The mechanisms further determine, based on the command, if precharging the memory cells following accessing the memory cells is to be inhibited. Moreover, the mechanisms send, in response to the determination indicating that precharging the memory cells is to be inhibited, a command to blocking logic of the DRAM structure to block precharging of the memory cells following accessing the memory cells.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elmootazbellah N. Elnozahy, Karthick Rajamani, William E. Speight, Lixin Zhang
  • Mechanisms for reducing DRAM power consumption
    Patent number: 8250298
    Abstract: Mechanisms are provided for inhibiting precharging of memory cells of a dynamic random access memory (DRAM) structure. The mechanisms receive a command for accessing memory cells of the DRAM structure. The mechanisms further determine, based on the command, if precharging the memory cells following accessing the memory cells is to be inhibited. Moreover, the mechanisms send, in response to the determination indicating that precharging the memory cells is to be inhibited, a command to blocking logic of the DRAM structure to block precharging of the memory cells following accessing the memory cells.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Karthick Rajamani, William E. Speight, Lixin Zhang
  • Data storage on a computer disk array
    Publication number: 20020199129
    Abstract: A method and a computer usable medium including a program for operating a plurality of disks. Units of data storage are selected. The disks are allocated between an active group and an inactive group. The units of data storage having a usage factor that meets a condition limit are allocated to the active group. The units of data storage having a usage factor not meeting the condition limit are allocated to the inactive group. The disks are selectively reallocated between the active group and the inactive group based upon a disk use parameter.
    Type: Application
    Filed: June 21, 2001
    Publication date: December 26, 2002
    Applicant: International Business Machines Corp.
    Inventors: Patrick J. Bohrer, Elmootazbellah N. Elnozahy, Charles R. Lefurgy, Ramakrishnan Rajamony, Bruce A. Smith
  • FAST REMOTE COMMUNICATION AND COMPUTATION BETWEEN PROCESSORS
    Publication number: 20120191946
    Abstract: A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
    Type: Application
    Filed: March 7, 2012
    Publication date: July 26, 2012
    Applicant: International Business Machines Corporation
    Inventors: John Bruce Carter, Elmootazbellah Nabil Elnozahy, Ahmed Gheith, Eric Van Hensbergen, Karthick Rajamani, William Evan Speight, Lixin Zhang
  • Method and system for compressing reduced instruction set computer (RISC) executable code through instruction set expansion
    Patent number: 6195743
    Abstract: A compression scheme is disclosed for program executables that run on Reduced Instruction Set Computer (RISC) processors, such as the PowerPC architecture. The RISC instruction set is expanded by adding opcodes to produce code that facilitates the removal of redundant fields. To compress a program, a compressor engine rewrites the executable using the new expanded instruction set. Next, a filter is applied to remove the redundant fields from the expanded instructions. A conventional compression technique such as Huffman encoding is then applied on the resulting code.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: February 27, 2001
    Assignee: International Business Machines Corporation
    Inventor: Elmootazbellah Elnozahy
  • FAST REMOTE COMMUNICATION AND COMPUTATION BETWEEN PROCESSORS
    Publication number: 20110296138
    Abstract: A method, system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventors: JOHN BRUCE CARTER, ELMOOTAZBELLAH NABIL ELNOZAHY, AHMED GHEITH, ERIC VAN HANSBERGEN, KARTHICK RAJAMANI, WILLIAM EVAN SPEIGHT, LIXIN ZHANG
  • Method and system for address trace compression through loop detection and reduction
    Patent number: 6347383
    Abstract: A method and system for compressing memory address traces based on detecting and reducing the loops that exist in a trace is disclosed. The method and system consists of two steps. In the first step, the trace is analyzed and loops are detected by determining the control flow among the program basic blocks. In the second step, each loop is analyzed to eliminate constant address references, and to apply compiler-like strength reduction on addresses that differ only by a fixed offset between consecutive loop iterations. Addresses that cannot be eliminated using the method and system of the present invention are kept in the trace.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: February 12, 2002
    Assignee: International Business Machines Corporation
    Inventor: Elmootazbellah Elnozahy
  • Technology for Web Site Crawling
    Publication number: 20140149382
    Abstract: A web site page has a reference for providing an address for a next page. The web site is crawled by a crawler program, which parses the reference from one of the web pages and sends the reference to an applet running in a browser. The address for the next page is determined by the browser responsive to the reference and is sent to the crawler. The crawler selects non-hypertext-link parameters from the web page of the web site server by performing a programmed action sequence, including selecting items from lists of the web page in a particular sequence. The crawler sends the applet running in the browser, for the query to the web server for the next page referenced by the one web page, the selected parameters and a context arising from the particular sequence.
    Type: Application
    Filed: January 30, 2014
    Publication date: May 29, 2014
    Applicant: International Business Machines Corporation
    Inventors: Elizabeth A. Brodsky, Elmootazbellah N. Elnozahy, Ramakrishnan Rajamony
  • ACCELERATING RECOVERY IN MPI ENVIRONMENTS
    Publication number: 20120226939
    Abstract: A computer usable program product for accelerating recovery in an MPI environment is provided in the illustrative embodiments. A first portion of a distributed application executes using a first processor and a second portion using a second processor in a distributed computing environment. After a failure of operation of the first portion, the first portion is restored to a checkpoint. A first part of the first portion is distributed to a third processor and a second part to a fourth processor. A computation of the first portion is performed using the first and the second parts in parallel. A first message is computed in the first portion and sent to the second portion, the message having been initially computed after a time of the checkpoint. A second message is replayed from the second portion without computing the second message in the second portion.
    Type: Application
    Filed: April 16, 2012
    Publication date: September 6, 2012
    Applicant: International Business Machines Corporation
    Inventor: ELMOOTAZBELLAH NABIL ELNOZAHY
  • Fast remote communication and computation between processors using store and load operations on direct core-to-core memory
    Patent number: 8799625
    Abstract: A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: John Bruce Carter, Elmootazbellah Nabil Elnozahy, Ahmed Gheith, Eric Van Hansbergen, Karthick Rajamani, William Evan Speight, Lixin Zhang
  • Power aware adaptive polling
    Publication number: 20040123169
    Abstract: A method for adapting the periodicity of polling for pending service requests, by polling system devices for pending service requests, recording whether or not there was a pending service request and, based on accumulated data, determining whether or not the system devices are idle. Based on this determination, the system may elect to enter a power conservation mode until device activity is signaled, or an adjustable period of time elapses. The adaptation mechanism may alter the periodicity of the timer interrupt, disable or enable device interrupts, and modify variables used to determine system idleness (including minimum latency and minimum idleness thresholds). In this manner, the system can conserve power while maintaining system performance and responsiveness.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 24, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elmootazbellah N. Elnozahy, Eric Van Hensbergen
  • ACCELERATING RECOVERY IN MPI ENVIRONMENTS
    Publication number: 20110296241
    Abstract: A method, system, and computer usable program product for accelerating recovery in an MPI environment are provided in the illustrative embodiments. A first portion of a distributed application executes using a first processor and a second portion using a second processor in a distributed computing environment. After a failure of operation of the first portion, the first portion is restored to a checkpoint. A first part of the first portion is distributed to a third processor and a second part to a fourth processor. A computation of the first portion is performed using the first and the second parts in parallel. A first message is computed in the first portion and sent to the second portion, the message having been initially computed after a time of the checkpoint. A second message is replayed from the second portion without computing the second message in the second portion.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: International Business Machines Corporation
    Inventor: ELMOOTAZBELLAH NABIL ELNOZAHY
  • RECOVERY IN SHARED MEMORY ENVIRONMENT
    Publication number: 20120226870
    Abstract: A method for recovery in a shared memory environment is provided in the illustrative embodiments. A core in a multi-core processor is designated as a user level core (ULC), which executes an instruction to modify a memory while executing an application. A second core is designated as a operating system core (OSC), which manages checkpointing of several segments of the shared memory. A set of flags is accessible to a memory controller to manage a shared memory. A flag in the set of flags corresponds to one segment in the segments of the shared memory. A message or instruction for modification of a segment is received. A cache line tracking determination is made whether a cache line used for the modification has already been used for a similar modification. If not, a part of the segment is checkpointed. The modification proceeds after checkpointing.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 6, 2012
    Applicant: International Business Machines Corporation
    Inventor: Elmootazbellah Nabil Elnozahy
  • Methods and arrangements to manage on-chip memory to reduce memory latency
    Publication number: 20060155886
    Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.
    Type: Application
    Filed: January 11, 2005
    Publication date: July 13, 2006
    Inventors: Dilma da Silva, Elmootazbellah Elnozahy, Orran Krieger, Hazim Shafi, Xiaowei Shen, Balaram Sinharoy, Robert Tremaine
  • Fast remote communication and computation between processors using store and load operations on direct core-to-core memory
    Patent number: 9934079
    Abstract: A system, and computer usable program product for fast remote communication and computation between processors are provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: April 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Bruce Carter, Elmootazbellah Nabil Elnozahy, Ahmed Gheith, Eric Van Hansbergen, Karthick Rajamani, William Evan Speight, Lixin Zhang
  • Architecture Support for Debugging Multithreaded Code
    Publication number: 20110258421
    Abstract: Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with the hardware unit is searched for an entry in the CAM corresponding to the target memory address. In response to an entry in the CAM corresponding to the target memory address being found, a determination is made as to whether information in the entry identifies the instruction as an instruction of interest. In response to the entry identifying the instruction as an instruction of interest, an exception is generated and sent to one of an exception handler or a debugger application. In this way, debugging of multithreaded applications may be performed in an efficient manner.
    Type: Application
    Filed: April 19, 2010
    Publication date: October 20, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elmootazbellah N. Elnozahy, Ahmed Gheith
  • Optimistic processing of network frames to reduce latency
    Publication number: 20020178068
    Abstract: A system and method in which the server device processes the lower level layers, referred to herein as the “network portion”, of a frame substantially in parallel with the processing of the application portion of the frame. The application portion of the frame, which may include an HTTP request is forwarded to the server application such as a web server, while the network portion of the frame is processed. If the processing of the network portion determines that the frame was mis-delivered or is corrupted, the response to the HTTP request is aborted, otherwise the response is processed and returned to the client. By optimistically assuming that the request was delivered correctly, the present invention leverages the parallel processing capabilities available on many server appliances and improve response time without incurring any substantial performance penalty.
    Type: Application
    Filed: May 24, 2001
    Publication date: November 28, 2002
    Applicant: International Business Machines Corporation
    Inventor: Elmootabellah Nabil Elnozahy
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