Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
Type:
Grant
Filed:
August 26, 2008
Date of Patent:
August 10, 2010
Assignees:
The Board of Trustees of the Leland Stanford Junior University, Canon Kabushiki Kaisha
Inventors:
Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
Type:
Grant
Filed:
March 8, 2010
Date of Patent:
April 5, 2011
Assignees:
Canon Kabushiki Kaisha, The Board of Trustees of the Leland Stanford Junior University
Inventors:
Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara
Abstract: Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices.
Type:
Grant
Filed:
July 22, 2005
Date of Patent:
February 24, 2009
Assignees:
Board of Trustees of the Leland Stanford Junior University, Canon Kabushiki Kaisha
Inventors:
Ammar Munir Nayfeh, Chi On Chui, Krishna C. Saraswat, Takao Yonehara