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  • ASYMMETRIC TRANSISTOR DEVICES FORMED BY ASYMMETRIC SPACERS AND TILTED IMPLANTATION
    Publication number: 20120171830
    Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.
    Type: Application
    Filed: March 12, 2012
    Publication date: July 5, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
  • ASYMMETRIC TRANSISTOR DEVICES FORMED BY ASYMMETRIC SPACERS AND TILTED IMPLANTATION
    Publication number: 20100078736
    Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.
    Type: Application
    Filed: September 2, 2009
    Publication date: April 1, 2010
    Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
  • Asymmetric transistor devices formed by asymmetric spacers and tilted implantation
    Patent number: 8574991
    Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: November 5, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
  • STRAIN ENGINEERING IN SEMICONDUCTOR DEVICES BY USING A PIEZOELECTRIC MATERIAL
    Publication number: 20150054083
    Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.
    Type: Application
    Filed: September 30, 2014
    Publication date: February 26, 2015
    Inventors: Stephan Kronholz, Maciej Wiatr
  • INCREASING STRESS TRANSFER EFFICIENCY IN A TRANSISTOR BY REDUCING SPACER WIDTH DURING THE DRAIN/SOURCE IMPLANTATION SEQUENCE
    Publication number: 20090246927
    Abstract: By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to conventional triple spacer approaches in forming drain and source regions of advanced MOS transistors.
    Type: Application
    Filed: November 14, 2008
    Publication date: October 1, 2009
    Inventors: Maciej Wiatr, Roman Boschke, Anthony Mowry
  • STRAIN ENGINEERING IN SEMICONDUCTOR DEVICES BY USING A PIEZOELECTRIC MATERIAL
    Publication number: 20100219719
    Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.
    Type: Application
    Filed: February 24, 2010
    Publication date: September 2, 2010
    Inventors: Stephan Kronholz, Maciej Wiatr
  • TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED BORON CONFINEMENT
    Publication number: 20100025743
    Abstract: By incorporating a diffusion hindering species at the vicinity of PN junctions of P-channel transistors comprising a silicon/germanium alloy, diffusion related non-uniformities of the PN junctions may be reduced, thereby contributing to enhanced device stability and increased overall transistor performance. The diffusion hindering species may be provided in the form of carbon, nitrogen and the like.
    Type: Application
    Filed: July 15, 2009
    Publication date: February 4, 2010
    Inventors: Jan Hoentschel, Maciej Wiatr, Vassilios Papageorgiou
  • FIELD EFFECT TRANSISTORS FOR HIGH-PERFORMANCE AND LOW-POWER APPLICATIONS
    Publication number: 20150200270
    Abstract: When forming semiconductor devices comprising high performance or low-power field effect transistors, the threshold voltage of the transistors is adjusted by the halo implantation and the source and drain regions are defined by a single implantation step. Thus, the number of process steps is reduced, whereas the electrical characteristics, such as leakage level, and performance of the transistors are maintained compared to conventional transistors.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 16, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Hermann Sachse, Maciej Wiatr
  • Asymmetric transistor devices formed by asymmetric spacers and tilted implantation
    Patent number: 8158482
    Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: April 17, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
  • COMPENSATION OF OPERATING TIME-RELATED DEGRADATION OF OPERATING SPEED BY A CONSTANT TOTAL DIE POWER MODE
    Publication number: 20100109757
    Abstract: By maintaining a substantially constant total die power during the entire lifetime of sophisticated integrated circuits, the performance degradation may be reduced. Consequently, greatly reduced guard bands for parts classification may be used compared to conventional strategies in which significant performance degradation may occur when the integrated circuits are operated on the basis of a constant supply voltage.
    Type: Application
    Filed: October 13, 2009
    Publication date: May 6, 2010
    Inventors: Maciej Wiatr, Richard Heller, Rolf Geilenkeuser
  • Strain engineering in semiconductor devices by using a piezoelectric material
    Patent number: 9263582
    Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Maciej Wiatr
  • Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence
    Patent number: 7923338
    Abstract: By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to conventional triple spacer approaches in forming drain and source regions of advanced MOS transistors.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: April 12, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Maciej Wiatr, Roman Boschke, Anthony Mowry
  • COLD TEMPERATURE CONTROL IN A SEMICONDUCTOR DEVICE
    Publication number: 20090295457
    Abstract: Operation of complex integrated circuits at low temperatures may be enhanced by providing active heating elements within the integrated circuit so as to raise the temperature of at least critical circuit portions at respective operational phases, such as upon power-up. Consequently, enhanced cold temperature performance may be obtained on the basis of existing process elements in order to provide design stability without requiring extensive circuit simulation or redesign of well-established circuit architectures.
    Type: Application
    Filed: February 23, 2009
    Publication date: December 3, 2009
    Inventors: Anthony Mowry, Casey Scott, Maciej Wiatr, Ralf Richter
  • Strain engineering in semiconductor devices by using a piezoelectric material
    Patent number: 8884379
    Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: November 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Maciej Wiatr
  • SOI DEVICE HAVING A SUBSTRATE DIODE FORMED BY REDUCED IMPLANTATION ENERGY
    Publication number: 20090111223
    Abstract: By removing material during the formation of trench openings of isolation structures in an SOI device, the subsequent implantation process for defining the well region for a substrate diode may be performed on the basis of moderately low implantation energies, thereby increasing process uniformity and significantly reducing cycle time of the implantation process. Thus, enhanced reliability and stability of the substrate diode may be accomplished while also providing a high degree of compatibility with conventional manufacturing techniques.
    Type: Application
    Filed: May 1, 2008
    Publication date: April 30, 2009
    Inventors: Maciej Wiatr, Markus Forsberg, Roman Boschke
  • SEMICONDUCTOR ELEMENT FORMED IN A CRYSTALLINE SUBSTRATE MATERIAL AND COMPRISING AN EMBEDDED IN SITU N-DOPED SEMICONDUCTOR MATERIAL
    Publication number: 20100327358
    Abstract: The PN junction of a substrate diode in a sophisticated semiconductor device may be formed on the basis of an embedded in situ N-doped semiconductor material thereby providing superior diode characteristics. For example, a silicon/carbon semiconductor material may be formed in a cavity in the substrate material, wherein the size and shape of the cavity may be selected so as to avoid undue interaction with metal silicide material.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 30, 2010
    Inventors: Stephan Kronholz, Roman Boschke, Vassilios Papageorgiou, Maciej Wiatr
  • Compensation of operating time-related degradation of operating speed by a constant total die power mode
    Patent number: 8456224
    Abstract: By maintaining a substantially constant total die power during the entire lifetime of sophisticated integrated circuits, the performance degradation may be reduced. Consequently, greatly reduced guard bands for parts classification may be used compared to conventional strategies in which significant performance degradation may occur when the integrated circuits are operated on the basis of a constant supply voltage.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: June 4, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Maciej Wiatr, Richard Heller, Rolf Geilenkeuser
  • METHOD FOR CREATING TENSILE STRAIN BY REPEATEDLY APPLIED STRESS MEMORIZATION TECHNIQUES
    Publication number: 20080237723
    Abstract: By introducing additional strain-inducing mechanisms on the basis of stress memorization techniques, the performance of NMOS transistors may be significantly increased, thereby reducing the imbalance between PMOS transistors and NMOS transistors. By amorphizing and re-crystallizing the respective material in the presence of a mask layer at various stages of the manufacturing process, a drive current improvement of up to approximately 27% has been observed, with the potential for further performance gain.
    Type: Application
    Filed: November 9, 2007
    Publication date: October 2, 2008
    Inventors: Andy Wei, Anthony Mowry, Andreas Gehring, Maciej Wiatr
  • METHOD FOR CREATING TENSILE STRAIN BY SELECTIVELY APPLYING STRESS MEMORIZATION TECHNIQUES TO NMOS TRANSISTORS
    Publication number: 20090142900
    Abstract: By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps.
    Type: Application
    Filed: May 20, 2008
    Publication date: June 4, 2009
    Inventors: Maciej Wiatr, Casey Scott, Andreas Gehring, Peter Javorka, Andy Wei
  • Semiconductor Devices Comprising a Channel Semiconductor Alloy Formed with Reduced STI Topography
    Publication number: 20120156846
    Abstract: In sophisticated semiconductor devices, a semiconductor alloy, such as a threshold adjusting semiconductor material in the form of silicon/germanium, may be provided in an early manufacturing stage selectively in certain active regions, wherein a pronounced degree of recessing and material loss, in particular in isolation regions, may be avoided by providing a protective material layer selectively above the isolation regions. For example, in some illustrative embodiments, a silicon material may be selectively deposited on the isolation regions.
    Type: Application
    Filed: July 27, 2011
    Publication date: June 21, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hans-Juergen Thees, Stephan Kronholz, Maciej Wiatr
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