Search Patents
  • Semiconductor wafer and method of producing the same
    Publication number: 20120306056
    Abstract: A semiconductor wafer (100) having a regular pattern of predetermined separation lanes (102) is provided, wherein the predetermined separation lanes (102) are configured in such a way that the semiconductor wafer is singularizable along the regular pattern.
    Type: Application
    Filed: May 17, 2012
    Publication date: December 6, 2012
    Applicant: NXP B.V.
    Inventors: Florian Schmitt, Heimo Scheucher, Michael Ziesmann
  • Semiconductor wafer and method of producing the same
    Patent number: 9754832
    Abstract: A semiconductor wafer (100) having a regular pattern of predetermined separation lanes (102) is provided, wherein the predetermined separation lanes (102) are configured in such a way that the semiconductor wafer is singularizable along the regular pattern.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: September 5, 2017
    Assignee: NXP B.V.
    Inventors: Florian Schmitt, Heimo Scheucher, Michael Ziesmann
  • Electro-acoustic transducer comprising an rfid circuit
    Publication number: 20070086605
    Abstract: In an electro-acoustic transducer (1), there are provided sound-generating means (38) of an annular form that surround an interior space (22), in which interior space (22) is housed an integrated circuit (31) by means of which a communication circuit (31B) of an RFID communication partner device (37) is formed.
    Type: Application
    Filed: November 12, 2004
    Publication date: April 19, 2007
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Heimo Scheucher
  • INTEGRATED CIRCUITS ON A WAFER AND METHOD OF PRODUCING INTEGRATED CIRCUITS
    Publication number: 20100155967
    Abstract: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).
    Type: Application
    Filed: July 10, 2008
    Publication date: June 24, 2010
    Applicant: NXP B.V.
    Inventor: Heimo Scheucher
  • Semiconductor wafer with process control modules
    Publication number: 20020117735
    Abstract: A semiconductor wafer (1) has a multitude of chips (5), of which chips (5) each one of a given number of chips (5) is situated in one of a multitude of adjacent exposure fields (2), and further has process control modules (4) which are each arranged in an exposure field (2), namely each in place of at least one chip (5).
    Type: Application
    Filed: February 21, 2002
    Publication date: August 29, 2002
    Applicant: U.S. PHILIPS CORPORATION
    Inventors: Joachim H. Schober, Heimo Scheucher, Paul Hubmer
  • Semiconductor wafer with process control modules
    Patent number: 6680523
    Abstract: A semiconductor wafer (1) has a multitude of chips (5), of which chips (5) each one of a given number of chips (5) is situated in one of a multitude of adjacent exposure fields (2), and further has process control modules (4) which are each arranged in an exposure field (2), namely each in place of at least one chip (5).
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: January 20, 2004
    Inventors: Joachim H. Schober, Heimo Scheucher, Paul Hubmer
  • Integrated circuits on a wafer and method of producing integrated circuits
    Patent number: 8264092
    Abstract: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: September 11, 2012
    Assignee: NXP B.V.
    Inventor: Heimo Scheucher
  • INTEGRATED CIRCUITS ON A WAFER AND METHODS FOR MANUFACTURING INTEGRATED CIRCUITS
    Publication number: 20100140748
    Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a plurality of integrated circuits (1a, 1b, 1c) formed on the wafer substrate (2). Each integrated circuit (1a, 1b, 1c) comprises an electric circuit (24) and some of the integrated circuits (1b, 1c) comprise, in addition to their electric circuits (24), process control modules (3) as integral parts. The process control modules (3) are employed during dicing and pick-and-place to align the dicing/pick-and-place devices.
    Type: Application
    Filed: July 10, 2008
    Publication date: June 10, 2010
    Applicant: NXP B.V.
    Inventor: Heimo Scheucher
  • Integrated circuits on a wafer and methods for manufacturing integrated circuits
    Patent number: 9620456
    Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a plurality of integrated circuits (Ia, Ib, Ic) formed on the wafer substrate (2). Each integrated circuit (Ia, Ib, Ic) comprises an electric circuit (24) and some of the integrated circuits (Ib, Ic) comprise, in addition to their electric circuits (24), process control modules (3) as integral parts. The process control modules (3) are employed during dicing and pick-and-place to align the dicing/pick-and-place devices.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: April 11, 2017
    Assignee: NXP B.V.
    Inventor: Heimo Scheucher
  • Wafer with improved sawing loops
    Patent number: 7576412
    Abstract: In a wafer (1) with chips (2) and elongate separating zones (4) between the chips (2), each chip (2) comprises at least one sawing loop (6), which sawing loop (6) comprises two protecting strips (17, 18) projecting from a planar protecting layer (16) of the chip (2), wherein said protecting strips (17, 18) are widened by means of wider strip portions (26, 27, 28, 29) where they emerge from the planar protecting layer (16), and wherein the protecting strips (17, 18) and the planar protecting layer (16) are provided with weak spots (31, 32, 34) serving as envisaged breakage points.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: August 18, 2009
    Assignee: NXP B.V.
    Inventor: Scheucher Heimo
  • Individual ROM codes on a single reticle for a plurality of devices
    Patent number: 8701077
    Abstract: Aspects of the present disclosure are directed toward methods and systems which generate a plurality of Read-Only Memory (ROM) codes. In response to generating the ROM codes, an image is generated for each of the plurality of ROM codes. The images for each of the plurality of ROM codes are mapped on a single reticle, and a wafer is provided, which includes a plurality of individual devices. The reticle is utilized, which includes an image for each of the plurality of ROM codes, to print a respective one of the images onto a respective one of the plurality of individual devices.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: April 15, 2014
    Assignee: NXP B.V.
    Inventors: Stefan Lemsitzer, Heimo Scheucher, Claus Grzyb
  • Chip Having Two Groups Of Chip Contacts
    Publication number: 20080017980
    Abstract: A chip (1) has a substrate (2), an integrated circuit (3) provided on the substrate (2), a plurality of conductor zones (ME1, ME2, ME3, ME4, ME5) and a passivating layer (5) provided to protect the conductor zones and the integrated circuit, through-holes (6, 7) being provided in the passivating layer (5) through which chip contacts (8, 9) are accessible, wherein additional chip contacts (10, 11) and connecting conductors (12, 13) are provided on the passivating layer (5) and wherein each additional chip contact has an electrically conductive connection to a chip contact via a connecting conductor.
    Type: Application
    Filed: May 18, 2005
    Publication date: January 24, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Heimo Scheucher
  • Chip having two groups of chip contacts
    Patent number: 9318428
    Abstract: A chip (1) has a substrate (2), an integrated circuit (3) provided on the substrate (2), a plurality of conductor zones (ME1, ME2, ME3, ME4, ME5) and a passivating layer (5) provided to protect the conductor zones and the integrated circuit, through-holes (6, 7) being provided in the passivating layer (5) through which chip contacts (8, 9) are accessible, wherein additional chip contacts (10, 11) and connecting conductors (12, 13) are provided on the passivating layer (5) and wherein each additional chip contact has an electrically conductive connection to a chip contact via a connecting conductor.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: April 19, 2016
    Assignee: NXP B.V.
    Inventor: Heimo Scheucher
  • DATA CARRIER COMPRISING STRAIN GAUGE MEANS
    Publication number: 20100225483
    Abstract: A data carrier (2) comprises a data circuit (4) arranged on a substrate (3) and data transmission means (10) being connected to the data circuit (4). The data carrier (2) further comprises at least one strain gauge means (7) being adapted to measure strains exerted on the substrate (3) and to transmit a deactivating signal (DE) to the data circuit (4) if the measured strains exceed a defined deactivating strain threshold. If the data circuit (4) receives the deactivating signal (DE), the data circuit (4) interrupts a data exchange with an external data reader/writer (1) via the data transmission means (10).
    Type: Application
    Filed: March 23, 2007
    Publication date: September 9, 2010
    Applicant: NXP B.V.
    Inventors: Heimo Scheucher, Ewald Bergler
  • Data carrier comprising strain gauge means
    Patent number: 7884722
    Abstract: A data carrier (2) comprises a data circuit (4) arranged on a substrate (3) and data transmission unit (10) being connected to the data circuit (4). The data carrier (2) further comprises at least one strain gauge unit (7) being adapted to measure strains exerted on the substrate (3) and to transmit a deactivating signal (DE) to the data circuit (4) if the measured strains exceed a defined deactivating strain threshold. If the data circuit (4) receives the deactivating signal (DE), the data circuit (4) interrupts a data exchange with an external data reader/writer (1) via the data transmission unit (10).
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: February 8, 2011
    Assignee: NXP B.V.
    Inventors: Heimo Scheucher, Ewald Bergler
  • Wafer With Improved Sawing Loops
    Publication number: 20080001259
    Abstract: In a wafer (1) with chips (2) and elongate separating zones (4) between the chips (2), each chip (2) comprises at least one sawing loop (6), which sawing loop (6) comprises two protecting strips (17, 18) projecting from a planar protecting layer (16) of the chip (2), wherein said protecting strips (17, 18) are widened by means of wider strip portions (26, 27, 28, 29) where they emerge from the planar protecting layer (16), and wherein the protecting strips (17, 18) and the planar protecting layer (16) are provided with weak spots (31, 32, 34) serving as envisaged breakage points.
    Type: Application
    Filed: July 20, 2005
    Publication date: January 3, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Heimo Scheucher
  • Chip Comprising at Least One Test Contact Configuration
    Publication number: 20080067509
    Abstract: In a chip (2) comprising a semiconductor body (6) and an integrated circuit (7) formed in the semiconductor body (6) and a passivation layer (14) designed to protect the integrated circuit (7) and a test contact configuration (15), the test contact configuration (15) has a test contact layer (16) lying below the passivation layer (14) and a test contact block (18) connected to the test contact layer (16), which test contact block (18) with a portion thereof projects through a hole (17) in the passivation layer (14) to the test contact layer (16) and is connected to the test contact layer (16), wherein the test contact block (18) has a contact region (20) lying above the passivation layer (14).
    Type: Application
    Filed: August 24, 2005
    Publication date: March 20, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Heimo Scheucher, Werner Puntigam, Thomas Burger
  • Integrated Circuits On A Wafer and Method For Separating Integrated Circuits On A Wafer
    Publication number: 20100270655
    Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a structure applied on a surface (4) of the wafer substrate (2). The structure forms a plurality of integrated circuits (1) formed on the wafer substrate (2) and the integrated circuits (1) are separated by saw lines (6, 7). The structure comprises a plurality of superposed layers (9a-9e) formed on the wafer substrate (2) and a top layer (10) formed on the superposed layers (9a-9e). The integrated circuit (1) on the wafer further comprise a plurality of alignment marks (3) intended for aligning a separating device (18) for separating the integrated circuits (1) on the wafer into individual integrated circuits (1) during a separation process, wherein the alignment marks (3) are formed from at least one of the superposed layers (9a-9e).
    Type: Application
    Filed: July 10, 2008
    Publication date: October 28, 2010
    Applicant: NXP B.V.
    Inventors: Heimo Scheucher, Guido Albermann, David Ceccarelli
  • Integrated circuits on a wafer and method for separating integrated circuits on a wafer
    Patent number: 8415769
    Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a structure applied on a surface (4) of the wafer substrate (2). The structure forms a plurality of integrated circuits (1) formed on the wafer substrate (2) and the integrated circuits (1) are separated by saw lines (6, 7). The structure comprises a plurality of superposed layers (9a-9e) formed on the wafer substrate (2) and a top layer (10) formed on the superposed layers (9a-9e). The integrated circuit (1) on the wafer further comprise a plurality of alignment marks (3) intended for aligning a separating device (18) for separating the integrated circuits (1) on the wafer into individual integrated circuits (1) during a separation process, wherein the alignment marks (3) are formed from at least one of the superposed layers (9a-9e).
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: April 9, 2013
    Assignee: NXP B.V.
    Inventors: Heimo Scheucher, Guido Albermann, David Ceccarelli
  • MAXIMIZING POTENTIAL GOOD DIE PER WAFER, PGDW
    Publication number: 20170092636
    Abstract: Consistent with an example embodiment, there is a semiconductor wafer substrate comprising a plurality of integrated circuits formed in arrays of rows and columns on the wafer substrate. A plurality of integrated circuits are in arrays of rows and columns on the wafer substrate; the rows and the columns have a first width. First and second saw lanes separate the integrated circuits, the first saw lanes are arranged parallel and equidistant with one another in a first direction defined by rows, and the second saw lanes are arranged parallel and equidistant with one another in a second direction defined by the columns. A plurality of process modules (PM) are on the wafer substrate, the PM modules defined in an at least one additional row/column having a second width. The at least one additional row/column is parallel to the plurality of device die in one direction.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 30, 2017
    Inventors: Tonny Kamphuis, Hans Cobussen, Heimo Scheucher, Laurentius de Kok
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