Abstract: A semiconductor wafer (100) having a regular pattern of predetermined separation lanes (102) is provided, wherein the predetermined separation lanes (102) are configured in such a way that the semiconductor wafer is singularizable along the regular pattern.

Abstract: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).

Abstract: A semiconductor wafer (1) has a multitude of chips (5), of which chips (5) each one of a given number of chips (5) is situated in one of a multitude of adjacent exposure fields (2), and further has process control modules (4) which are each arranged in an exposure field (2), namely each in place of at least one chip (5).

Abstract: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a plurality of integrated circuits (1a, 1b, 1c) formed on the wafer substrate (2). Each integrated circuit (1a, 1b, 1c) comprises an electric circuit (24) and some of the integrated circuits (1b, 1c) comprise, in addition to their electric circuits (24), process control modules (3) as integral parts. The process control modules (3) are employed during dicing and pick-and-place to align the dicing/pick-and-place devices.

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a structure applied on a surface (4) of the wafer substrate (2). The structure forms a plurality of integrated circuits (1) formed on the wafer substrate (2) and the integrated circuits (1) are separated by saw lines (6, 7). The structure comprises a plurality of superposed layers (9a-9e) formed on the wafer substrate (2) and a top layer (10) formed on the superposed layers (9a-9e). The integrated circuit (1) on the wafer further comprise a plurality of alignment marks (3) intended for aligning a separating device (18) for separating the integrated circuits (1) on the wafer into individual integrated circuits (1) during a separation process, wherein the alignment marks (3) are formed from at least one of the superposed layers (9a-9e).

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a structure applied on a surface (4) of the wafer substrate (2). The structure forms a plurality of integrated circuits (1) formed on the wafer substrate (2) and the integrated circuits (1) are separated by saw lines (6, 7). The structure comprises a plurality of superposed layers (9a-9e) formed on the wafer substrate (2) and a top layer (10) formed on the superposed layers (9a-9e). The integrated circuit (1) on the wafer further comprise a plurality of alignment marks (3) intended for aligning a separating device (18) for separating the integrated circuits (1) on the wafer into individual integrated circuits (1) during a separation process, wherein the alignment marks (3) are formed from at least one of the superposed layers (9a-9e).

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2), a plurality of integrated circuits (1) formed lattice-like in rows and columns on the wafer substrate (2), and first and second saw lines (4, 5) separating the integrated circuits (1). The first saw lines (4) run parallel and equidistant with respect to each other in a first direction (x) defined by the rows and the second saw lines (5) run parallel and equidistant with respect to each other in a second direction (y)defined by the columns. The integrated circuits (1) on the wafer further comprise a plurality of process control modules (3) formed on the wafer substrate (2) such that a given process control module (3) of the plurality of process modules (3) is bounded by two consecutive first saw lines (4) as well as by two consecutive second saw lines (5).