Abstract: In a chip (2) comprising a semiconductor body (6) and an integrated circuit (7) formed in the semiconductor body (6) and a passivation layer (14) designed to protect the integrated circuit (7) and a test contact configuration (15), the test contact configuration (15) has a test contact layer (16) lying below the passivation layer (14) and a test contact block (18) connected to the test contact layer (16), which test contact block (18) with a portion thereof projects through a hole (17) in the passivation layer (14) to the test contact layer (16) and is connected to the test contact layer (16), wherein the test contact block (18) has a contact region (20) lying above the passivation layer (14).

Abstract: In an integrated circuit (1) having a substrate (3) and having a signal-processing circuit (4) which is produced at a surface (8) of the substrate (3), there is provided on the substrate surface (8) a protective layer (12) that has at least one aperture (13) through which a second contact pad (14) is electrically and mechanically connected to a first contact pad (9), wherein the second contact pad (14) is of a height of at least 15 ?m and projects laterally beyond the aperture (13) on all sides and is seated on the protective layer (12) by an overlap zone (z) that is closed on itself like a ring, wherein the overlap zone (z) has a constant width of overlap (w) of between 2 ?m and 15 ?m, and wherein at least one element of the signal-processing circuit (4), and preferably only one capacitor (5) of the signal-processing circuit (4), is provided opposite the first contact pad (9).