Abstract: A NAND flash memory structure with a wordline or control gate that provides shielding from Yupin effect errors and generally from potentials in adjacent strings undergoing programming operations with significant variations in potential.

Abstract: A NAND flash memory structure with a wordline or control gate that provides shielding from Yupin effect errors and generally from potentials in adjacent strings undergoing programming operations with significant variations in potential.

Abstract: A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed.

Abstract: An error recovery technique is used on marginal nonvolatile memory cells. A marginal memory cell is unreadable because it has a voltage threshold (VT) of less than zero volts. By biasing adjacent memory cells, this will shift the voltage threshold of the marginal memory cells, so that it is a positive value. Then the VT of the marginal memory cell can be determined. The technique is applicable to both binary and multistate memory cells.

Abstract: An error recovery technique is used on marginal nonvolatile memory cells. A marginal memory cell is unreadable because it has a voltage threshold (VT) of less than zero volts. By biasing adjacent memory cells, this will shift the voltage threshold of the marginal memory cells, so that it is a positive value. Then the VT of the marginal memory cell can be determined. The technique is applicable to both binary and multistate memory cells.

Abstract: Program disturb in a Flash storage array is reduced by applying a voltage level that depends on the threshold level of a previously programmed cell to the word-line of that cell during programming of subsequent cells on the same bit-line. By applying higher voltages to word-lines containing unselected programmed memory cells with higher threshold voltages, program disturb due to these higher threshold cells is reduced.

Abstract: A technique to perform an operation (e.g., erase, program, or read) on memory cells (105) is to apply an operating voltage dynamically to the gates (111, 113) of the memory cells, rather than a continuous operating voltage. This reduces the power consumed during the operation. Dynamic operation or background operation such as background erase also permits other operations, such as read, program, or erase, to occur while the selected memory cells are operated on. This improves the operational speed of an integrated circuit using dynamic operation compared to a continuous operation.

Abstract: A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed by a voltage applied to the common line are caused to electrically float while the source and drain regions of memory cells not being programmed have voltages applied thereto. This programming technique is applied to large arrays of memory cells having either a NOR or a NAND architecture.

Abstract: Non-volatile memory such as flash EEPROM has memory cells that may be programmed in parallel using a self-limiting programming technique. Individual cells have charge storage units that may be charged by hot electrons in a self-limiting manner. As the charge storage unit reaches the required level of charge, hot electrons are no longer generated, or are generated in reduced number. The level of charge at which hot electron generation stops is determined by the voltage applied to the cell. Thus, several cells may be programmed in parallel, each self-limiting at a charge level corresponding to the voltage applied.

Abstract: A programming technique for a flash memory causes electrons to be injected from the substrate into charge storage elements of the memory cells. The source and drain regions of memory cells along a common word line or other common control gate line being programmed by a voltage applied to the common line are caused to electrically float while the source and drain regions of memory cells not being programmed have voltages applied thereto. This programming technique is applied to large arrays of memory cells having either a NOR or a NAND architecture.

Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Abstract: Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Abstract: In a non-volatile memory system, when it is discovered that the voltage pump pulse provided by a charge pump for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the end of the programming cycle. In this manner, the fluctuation in the effective programming time period of the programming pulses is prevented for the remainder of the programming cycle so that a broadening of the threshold voltage distribution will not occur or will be reduced. This feature allows a short programming time period to be designated for the programming pulses for enhanced performance, while allowing the flexibility of increased program time period when the charge pump is operating under conditions that causes it to be slow and/or weak.

Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Abstract: In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold voltage. This can be prevented by modifying the programming scheme so that this does not occur. In one implementation, this is accomplished by choosing a code scheme, which does not cause the memory cells to be programmed to the wrong threshold voltage during the second programming pass, or by programming the memory cells in accordance with substitute data that would not cause the cells to be programmed to an erroneous state.

Abstract: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.

Abstract: A technique to perform an operation (e.g., erase, program, or read) on memory cells (105) is to apply an operating voltage dynamically to the gates (111, 113) of the memory cells, rather than a continuous operating voltage. This reduces the power consumed during the operation. Dynamic operation or background operation such as background erase also permits other operations, such as read, program, or erase to occur while the selected memory cells are operated on. This improves the operational speed of an integrated circuit using dynamic operation compared to a continuous operation. A transfer transistor controls coupling of the operating voltage to a node of the memory cells selected for dynamic operation. When the node is substantially charged to the operating voltage it is floated by turning off the transfer transistor. The dynamically held operating voltage is allowed to perform the memory operation with the occasional refresh.

Abstract: Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.