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  • Synchronous dram having a plurality of latency modes
    Patent number: 5835956
    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).
    Type: Grant
    Filed: March 17, 1997
    Date of Patent: November 10, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Churoo Park, Hyun-Soon Jang, Chull-Soo Kim, Myung-Ho Kim, Seung-Hun Lee, Si-Yeol Lee, Ho-Cheol Lee, Tae-Jin Kim, Yun-Ho Choi