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  • Patent number: 7622372
    Abstract: Vacancies and dopant ions are introduced near the surface of a semiconductor layer structure. Implanted dopant ions which diffuse by an interstitialcy mechanism have diffusivity greatly reduced, which leads to a very low resistivity doped region and a very shallow junction.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: November 24, 2009
    Inventors: Wei-Kan Chu, Lin Shao
  • Patent number: 7105427
    Abstract: Vacancies and dopant ions are introduced near the surface of a semiconductor wafer. The dopant ions which diffuse by an interstitialcy mechanism have diffusivity greatly reduced, which leads to a very low resistivity doped region and a very shallow junction.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: September 12, 2006
    Inventors: Wei-Kan Chu, Lin Shao, Xinming Lu, Jiarui Liu, Xuemei Wang
  • Publication number: 20040018703
    Abstract: A method of forming a stable junction on a microelectronic structure on a semiconductor wafer having a silicon surface layer on a substrate includes the following steps: implanting dopant ions into the surface layer; cleaning and oxidizing the surface layer, and twice annealing the wafer to recover a damaged silicon crystal structure of the surface layer resulting from the low energy ion implantation. The first annealing process uses a temperature range of 800° C. to 1200° C. for a duration from about a fraction of a second to less than about 1000 seconds, with a ramp-up rate of about 50° C./second to about 1000° C./second. The second annealing process uses a temperature range of 400° C. to 650° C. for a time period of from about 1 second to about 10 hours, and more preferably, from about 60 seconds to about 1 hour. Both annealing processes include cooling processes.
    Type: Application
    Filed: July 17, 2003
    Publication date: January 29, 2004
    Applicant: University of Houston
    Inventors: Wei-Kan Chu, Lin Shao, Jiarui Liu
  • Patent number: 6835626
    Abstract: A method of forming a stable junction on a microelectronic structure on a semiconductor wafer having a silicon surface layer on a substrate includes the following steps: implanting dopant ions into the surface layer; cleaning and oxidizing the surface layer, and twice annealing the wafer to recover a damaged silicon crystal structure of the surface layer resulting from the low energy ion implantation. The first annealing process uses a temperature range of 800° C. to 1200° C. for a duration from about a fraction of a second to less than about 1000 seconds, with a ramp-up rate of about 50° C./second to about 1000° C./second. The second annealing process uses a temperature range of 400° C. to 650° C. for a time period of from about 1 second to about 10 hours, and more preferably, from about 60 seconds to about 1 hour. Both annealing processes include cooling processes.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: December 28, 2004
    Assignee: University of Houston
    Inventors: Wei-Kan Chu, Lin Shao, Jiarui Liu