Abstract: A gunn transceiver logic input circuit for use in a semiconductor memory device is capable of effectively inputting a signal having a small voltage difference. The gunn transceiver logic input circuit includes first and second input units which respectively input a GTL-level input signal and a GTL-level reference signal. First and second generating units with first and second level shifters respectively shift the GTL-level input signal and GTL-level reference signal to the ECL-level. An ECL buffer circuit compares the voltages between the ECL-level input signal and the ECL-level reference signal and generates first and second ECL-level output signals while maintaining a swing width of the GTL level signal.

Abstract: A semiconductor integrated circuit has an integrally formed logic circuit that is controlled by clock signals. The semiconductor integrated circuit includes a clock signal delay device that generates a plurality of clock signals having phases that are shifted from each other by a small amount with respect to a reference clock signal. The logic circuit is divided into a plurality (N number) of circuit blocks so that each of the circuit blocks is controlled by each of the associated plurality of clock signals to reduce noises. Noises in a CMOS integrated circuit are also reduced by controlled reference clock signals. A CMOS integrated circuit includes at least one CMOS gate with an input terminal being commonly connected to gates of a PMOS transistor and an NMOS transistor, and a latch circuit for transmitting data to the input terminal of the CMOS gate by clock signal control.