Abstract: Even if an element such as a ROM is not used, a code reverse conversion can be realized by a sufficiently small scale circuit to be effective for integration. When code data group converted from 8-bit to 15-bit according to a predetermined rule is converted to original 8-bit code data group, an exclusive logic processor 11, a bit shift processor 12, a six-to-four decoder and an eleven-to-eight decoder 14 divides the 15(m) bit code (dividing by m at the maximum) into a plurality of areas, converts "1" (in the case of positive logic) in response to the generated bit position in the respective areas, and the numeric codes obtained by the numeric value converting means are added by an adder 15.

Abstract: A code table apparatus for a variable length decoder (VLD) is disclosed. The code table apparatus is connected to a barrel shifter to obtain an input code which consists of a code word portion and a sign bit. The code table apparatus comprises a coefficient table for generating a level code and a length code by the code word portion, and a mask circuit for generating a sign bit by a logic operation of the input code and the length code. The coefficient table can decode input codes with opposite sign bits, thus reducing the dimensions of the coefficient table as well as the VLD. Furthermore, since the dimensions of the coefficient table are reduced, the operation time delay of the DCT coefficient table can be shorter, thus improving the performance of the VLD.