Abstract: A display device comprises a display panel, a scanning circuit section for supplying a scanning signal to scanning lines of the display panel, and a scanning control circuit section for supplying an n-bit (n: 2 or more positive integer) input numeral signal and an inverted replica of the input numeral signal to the scanning circuit section. In the display device, a scanning circuit section comprises an input connection line group having sets of input connection lines for receiving bits of the input numeral signal and bits of the inverted replica of the input numeral signal, a plurality of logic circuit sections, less in number than the scanning lines, for responding to combinations of the input numeral signal and its inverted replica, and an output distributing unit for assigning an output from one logic circuit section to at least two scanning lines.

Abstract: A display device comprises a display panel, a scanning circuit section for supplying a scanning signal to scanning lines of the display panel, and a scanning control circuit section for supplying an n-bit (n: 2 or more positive integer) input numeral signal and an inverted replica of the input numeral signal to the scanning circuit section. In the display device, a scanning circuit section comprises an input connection line group having sets of input connection lines for receiving bits of the input numeral signal and bits of the inverted replica of the input numeral signal, a plurality of logic circuit sections, less in number than the scanning lines, for responding to combinations of the input numeral signal and its inverted replica, and an output distributing unit for assigning an output from one logic circuit section to at least two scanning lines.

Abstract: A liquid crystal display includes a matrix array of liquid crystal pixels, data lines formed along columns of the pixels, TFTs assigned to the pixels for causing the data lines to be electrically connected to the pixels of a selected row, and a data line driver which drives the data lines and has a first video bus for transmitting analog pixel signals of the positive polarity for the pixels of one of odd and even columns in a selected row, a second video bus for transmitting analog pixel signals of the negative polarity for the pixels of the other one of the odd and even columns in the selected row, sample-hold units each assigned to adjacent two of the data lines to simultaneously sample-hold the pixel signals on the first and second video buses, and a shift register circuit for enabling the operations of the sample-hold units sequentially.