Abstract: A small first level cache and large second level cache support a central processor in accessing necessary data for processing. The second level cache holds tag address words each having two status bits V and R. The V bit indicates validity/invalidity status while the R bit informs the second level cache of the validity/invalidity status of the corresponding address in the first level cache. As a result of the status information between the two caches, the spy-snoop operation and invalidation operation cycles are minimized as to the use required of the processor bus, enabling higher efficiency processor operations. Utilization is made of a smart-fill algorithm which selects the address locations for placement of new data in a second level cache for a Write operation and after a Read-Miss by analyzing the status values (V,R) for each address in order to minimize the overwriting of valid cache data.

Abstract: A method for message transfers between digital modules in a network where some modules are hardware implemented and some modules are emulated in software. An Auxiliary Message Arbitrator Unit utilizes Main Memory storage for messages destined for receiving modules. Algorithmic sequencing means maintains chronological transfer operations of messages and uses hard and soft Interrupt signal queues to inform respective hard and soft modules of pending messages for them to retrieve.

Abstract: A system and method for transforming specialized data files of a first computer system into industry-standard byte-stream files usable for a second system or other systems. First and second programmatic interfaces of the first system can take the specialized format native data files and transform them into standard formatted byte-stream data files for placement in a storage media of a second computer system which can then be initiated to use a CD Writer package to cause the data files to burned on to a CD-ROM. This CD-ROM can then provide the byte-stream data file for use in many different types of platforms.

Abstract: A method and system of message transfers in a multiple sender-multiple receiver network provides a specialized sequence for a Sender to acquire a message slot and place a message in a message queue, and a retrieval sequence for the Receiving module that insures message transmission integrity and proper chronological sequence of message delivery.

Abstract: A system and method for developing a digital control signal Y for setting a target module (D) according to a digital setpoint signal A, a digital feedback signal C, a difference digital signal X=A-C in an exponential relationship, such that Y=2.sup.X+1 -1. An N bit digital signal X is translated exponentially via a simple, non-complex programmable array logic unit to an expanded N+q digital bit signal providing an exponentially expanded response for the control signal Y to reset the target module D to an optimally desired setting.

Abstract: A system and method in a digital network for developing a digital output control signal Y which is of greater range and sensitivity than an input digital difference signal X wherein Y has a linear functional relationship to X according to a slope parameter "b". A method is developed for implementing the network with Field Programmable Gate Arrays (FPGAs) to develop the output control signal Y equal to a+bX on an expanded digital bus, where "a" is the intercept value of Y when X=0.

Abstract: A two domain digital network with each domain having its own system bus and its own bus exchange module permits Write operation addresses to be passed between domains. Each bus exchange module provides a match filter which prevents the passage from one bus to the other bus of a duplicate Write operation (OP) address which has already been transferred, thus relieving the busses of excess traffic when a duplicate Write OP address is being sent to a cache memory for an invalidation operation. A Read operation will nullify the match filter to then allow passage of each incoming Write OP invalidation address to the snoop invalidation queue, but prevent the passage of a subsequent duplicate Write OP address, so long as the read OP is ongoing.

Abstract: A network providing a server using an object-database enables an author to create and store an original document, as a source file with a first format. Software in the data base will provide multiple sets of shadow file-converter groups connected to the source file of the original document. Each shadow file-converter set enables the transformation of the original source file format into a particular other specific type of format. Any client or user of the network can access and receive a copy of the original source document which is automatically reformatted to match the requirements of the receiver's appliance. Thus, one original source document can be created and then published in any specific format to multiple numbers of and type of receiving appliances.

Abstract: A computer network serviced by a maintenance subsystem holds a control processing module (CPM) holding a Data Path Array as interface to a main memory module and I/O Module. A maintenance controller in the CPM has a preloaded Flash Memory unit holding all the necessary operating addresses and data which can be rapidly transferred via a special wide parallel high speed data bus to a data path array unit for subsequent conveyance to a channel microcode block in a main memory module. The operating data include channel microcode data necessary for the I/O Module to communicate with different types of peripheral devices.

Abstract: A central processing module (CPM) uses a data path array interface connecting dual system busses to a main memory module and I/O module. A maintenance controller in the CPM manages a programmable array logic unit controller to read out microcode words in the main memory module to verify their accuracy by comparison with an original data base of microcode words in a flash memory which was earlier pre-loaded from a maintenance subsystem. A high speed auxiliary data bus controlled by the programmable array logic controller, provides a high speed transfer channel for moving the main memory words to the maintenance controller which can then institute a verification procedure for each memory word.

Abstract: A content server using an object database supports a network of multiple User clients. The database is loaded with virtual objects which constitute source documents in the form of a multiplicity of resource objects, which may be file-oriented objects or message-oriented objects, which enable the format of any source document to be converted to another format compatible for transport via an appropriate protocol to a requesting client User. The resource objects include a multiplicity of converter objects which are defined and placed in the database to provide format transformation from the format of the original source document content into the format required by a calling requester. The object database will be searched to find the proper converter object to transform the contents of the source document into the required format for the calling requester's facilities or for transmittal to a digital appliance in a protocol appropriate to the receiving requester or digital appliance.

Abstract: A computer architecture where a processor with store-through cache is linked with a cache control module, a bus interface to dual system busses, a system spy module monitoring the dual system busses for new data overwrites and an invalidation queue for holding cache addresses to be invalidated while the entire network is controlled by a programmable state machine system for enabling cache access and cache invalidation operations.

Abstract: A hardware message transfer control unit designated as the Auxiliary Message Arbitrator Unit (AMA) manages message transfers and transfer protocols in a network of sending and receiving digital hardware modules. Flexibility of network expansion to include software emulated digital modules to the hardware modules is provided in RAM circuitry at the message transfer control unit.

Abstract: A multi-set cache structure, providing a first-level cache and second level cache to a processor, stores data words where each word holds two bytes and two status bits. Each cache set includes a Tag RAM for holding the address data words and a Parity RAM holding a parity bit for each byte and a parity bit for the two status bits. A programmable array logic control unit has a predictive generator logic unit to generate the proper "status parity bit" for each set of status bits (V,R) without need for waiting to calculate the status parity bit from the existing values of the two status bits.

Abstract: A computer network having a Control Processing Module (CPM) maintained by an external Maintenance Subsystem where the CPM has JTAG compatible digital units, but where the Cache Module is not JTAG compatible. Specialized transceivers having Boundary Scan Registers are activated to enable loading of address words in a Tag RAM while concomitantly placing correct initial parity data in a Parity RAM without need to continue communication with the external Maintenance Subsystem. The Boundary Scan Registers in said transceivers are set up to perform as up-counters to sequence through all address locations in the Tag RAM while a Control PAL calculates and places the associated parity values in each corresponding address location in the Parity RAM.

Abstract: A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through cache memory which includes interface modules including a spy unit for maintaining cache coherency and arbiter modules so that any particular module is not starved out. A maintenance processor organizes the network as a joined system where both the store-through and non-store through processor units can utilize either one of the dual system busses or a split system where one bus is dedicated to the store-through processor units and one bus is dedicated to the non-store through processor units.

Abstract: A system and method for setting the sequence of processor operations in real time depending on the nature of Write commands and Send Message Commands in waiting queues which are ordinarily sequenced with Read OPs according to the sequential order that the commands are received. The system will give bus access to Read commands ahead of the Write commands and other commands in the waiting queues as long as data coherency will not be affected. Thus, the sequence of bus access can be modified to a different sequence giving priority-of-access to Read commands.

Abstract: A network in which an incoming word of 4 bytes and 4 parity bits is split into an address pointer and Tag address data into a Tag RAM storing two bytes which do not align with the incoming bytes and which leave a 2-bit (x,y,) crossed field. A programmable array logic Control PAL places correct parity values into a Parity RAM for the 2 stored bytes and later recreates the original word of 4 bytes and parity bits by using a flip-bit value (SPX) which simplifies the regeneration of correct parity values.

Abstract: A two domain network linking a first and second data processing system enables efficient data transfers between modules in the first system and modules in the second system through linkage by bus exchange modules having message queues and snoop-write address queues in each domain. Each system also allocates bus access using a selectively adjusting bus access priority arbitration logic unit. The Snoop-Write address queues in each bus exchange module can temporarily hold a sequence of Write OP addresses snooped from one domain for invalidation in another domain without requiring the bus exchange module to dominate its access priority over other requesting modules.

Abstract: A system and method for enhancing the rapidity of invalidation cycles in a processor having store-through cache holding 4-word data packets whereby an invalidation queue holds addresses of data to be invalidated in cache and the addresses are supplied by a system bus spy module which monitors the addresses of new data words selected for a write operation.