Abstract: A network comprising a central processing module and maintenance subsystem which provides a system for rapid loading of instruction words in a microcode RAM whereby microcode instruction words from the maintenance subsystem are preliminarily loaded into a flash memory in the central processing module. A maintenance controller transfers the microcode instruction words from the flash memory over a transfer bus to a data path array which connects to a processor-instruction memory bus for enabling microcode addresses and data words to be rapidly transferred into a microcode RAM instruction memory. A programmable controller activated by the maintenance controller in the central processing module then regulates the transfer of data to the microcode RAM by providing incrementation of the addresses of the instruction words on an automatic basis and thus relieving the processor of this function.

Abstract: An optimization system for the cache-fill operation in a multi-set cache memory operates to select that cache-set which indicates it has invalid data therein and/or also indicates that an associated upper level cache has correspondingly invalid data. When no data invalidity is indicated, then a random counter is used to arbitrarily select an address for one set of the multiple-set cache units for the data-fill operation.

Abstract: An initiator-sending module requests bus access on a retry-basis after a "bus-error" or "receiver-not ready" situation. The bus request retry is provided with an adjustable wait delay period tailored to the specific system and provides a programmable random wait delay which also includes a minimum time delay period programmed for that specific system network.

Abstract: A computer network is connected via dual system busses to multiple digital modules such as a Central Processing Module with a Central Processor and also to a main memory module, plus an I/O module in addition to other possible modules, such as other Central Processing Modules. The Central Processor has a cache memory which is accessed on the basis of adjustable priorities, the most normal situation being that the Central Processor has first priority to cache access. However, under certain other conditions, the priority of access to cache is adjusted to give priority to an invalidation queue when it is almost full of invalidation addresses to be processed on invalidation cycles to the cache memory. Another priority is given to the invalidation queue after a Read-Lock operator is initiated by the processor. The resulting adjustable priorities work to optimize the integrity and speed of throughput of the system.

Abstract: A system and method for using standard JTAG protocol for testing protocol compliant and non-protocol compliant digital devices without altering the JTAG protocol or the non-compliant device. A specialized Test Access Port Controller controls and monitors the states applied to the non-compliant device in order to eliminate the PAUSE state in the non-compliant device and to limit the Run-Test/Idle state to one clock period.

Abstract: A digital system which normally initializes and tests non-JTAG logic units is adapted to test JTAG protocol compatible logic units. A JTAG translator unit provides an instruction control register and a Data Register. The Control Register has control bits for selecting Test-Mode-Select and Test Clock signals for the JTAG compatible units and Shift/Hold signals for the non-JTAG compatible logic units. The Data Register supplies diagnostic test bits to registers in both the JTAG and non-JTAG logic units. Additionally, the Control Register can initiate automatic incrementation of addresses to a control state RAM for rapid loading of microcode.

Abstract: An arbitration logic system in a system control module regulates access to a common system bus as provided by a state machine which toggles access priority between two or more resource modules while preventing deadlock contention between two requesting modules while insuring that no module will be starved or denied access even though all the resource modules are contending for bus access. Any continuous deprivation or starvation of a module for bus access is prevented, in addition to any deadlock situations which are also prevented. This occurs by allowing retrying modules to request the bus at a temporarily higher priority and limiting the number of retries that any given requesting module is permitted to have.

Abstract: A system whereby a microcode RAM in a central processing module can have each microcode word rapidly accessed and transferred to a maintenance controller to compare each accessed microcode word with a corresponding microcode word in a set of microcode words which were pre-loaded in a flash memory.

Abstract: A central processor is serviced by a multi-way cache module having N cache sets some of which can be taken off-line by a maintenance subsystem. Masking logic is provided to control the fill-operation cycles to cache so that equitable distribution of fill-data is allocated among only those cache sets remaining on-line.

Abstract: A system for interleaving invalidation cycles to a cache memory during those periods when the processor is waiting or has not need to access cache memory. These periods occur during a Read-Miss operation or when bus access delays to main memory cause the processor to wait for receipt of data, or when the processor communicates with network modules other than the cache memory and main memory.

Abstract: A state machine system is used to control a cache controller in a network involving the operations of a processor having a store-through cache and operations involving an invalidation queue which is filled by a spy module which monitors dual system busses to select addresses of words which appear for write operations.

Abstract: A FIFO invalidation queue for address words, from a spy module, are held for subsequent invalidation operations to a cache memory. The FIFO queue is programmably organized to indicate when it is almost full in which case it will switch to a priority operation which will give priority to invalidation cycles in the cache over the priority of the processor's cache access. When the FIFO queue indicates that it is almost empty, then the priority of the cache access by the processor is re-established as it was in normal conditions. The system operates concurrently in a self-regulating manner to load and unload addresses into the FIFO queue while also giving priority to flushing out the queue with invalidation cycles when preset upper limits are reached.

Abstract: A field programmable gate array circuit device provides a bus interface data path between a processor and system bus, each of which operates at a different data transfer protocol at a different clock rate. The bus interface unit controls the transfer of data to and from a system bus which is connected to a main memory module, an I/O module or other modules, such as an external CPM module. Data passing from various modules to the processor or from the processor to various modules can operate in one word or four-word blocks. Additionally, intermodule communication is managed by message words, which message words are operative in groups of four words as a block. A transfer logic box holds a plurality of (i) Request words (ii) Acknowledgement words for conveyance to the processor from external modules.

Abstract: A multi-set cache module is initiated by a maintenance subsystem to function with all sets on-line or only some sets on-line. A parity error sensing switch flip-flop unit will selectively disable only those sets which indicate parity error problems except when multiple simultaneous "hit" signals occur, in which case, the switch unit disables all of the cache sets.

Abstract: Two partitioned systems are interconnected by bus exchange modules which connect to first and second system common busses. Each system common bus shares three or more requestors, and an arbitration logic unit in each partition manages bus access priority depending on certain existing conditions. Equitable access to each system bus is allocated and no one particular requestor will be locked out from bus access. Deadlock and starvation are prevented by setting one requestor module for normal top priority but also allocating secondary priority to the remaining two requestor modules by toggling and rotating priorities among these two requestor modules. Additionally, the arbitration logic allows the two requester retrying modules to request the bus at a temporarily higher priority, but limiting the number of retry cycles allowed to any given requesting module.

Abstract: A maintenance interface system for testing the Logic states of circuitry in digital modules provides for selecting a snake data path and using its control to Write into or to Read out in a forward sequence or selectively in a reverse sequence.

Abstract: An enhanced computer system architecture provides a processor supported by a general cache and a mini-cache wherein the mini-cache will supply requested data words not available in the general cache thus eliminating the extra clock periods necessary to access main memory. The mini-cache stores frequently used data words and is refilled concurrently during processor command execution and is settable for handling data words or code words or both. A data queue storage stores a block of words which duplicate words in main memory. If the requested address matches an address register block in the mini-cache, the data queue store will make the words in the data queue available to requests from the processor. The mini-cache also monitors the system bus for any "write" operations which might change the validity of the data in the address register block of the mini-cache. In this case, the data stored in the mini-cache is invalidated and cannot be used by the processor.

Abstract: A microcode cache memory is provided on a processor chip for supplying frequently used microcode instruction words to a processor. A bank of multiple Tag-Status RAMs holds addresses of microcode words residing in a bank of Data RAMs. A state machine and a special Least Recently Used Random Access Memory (LRU RAM) operate to maintain the more frequently used words in the Data RAMs so that more hits occur to provide the requested word in one clock cycle. A 90 bit microcode word with 20 fields enables the processor to perform multiple functions simultaneously in parallel.

Abstract: The logic circuitry of an IC chip is connected to JTAG register chains which hold state information on each portion of the logic circuitry therein. A JTAG Tracker Module is connected to the controls of each of the JTAG register chains enabling a programmer-operator to read the present state of each JTAG register chain and enabling a readout of the logic circuits condition in a single clock period.

Abstract: By expanding the cache address invalidation queue into bit slices for holding odd invalidation addresses and even invalidation addresses and also by providing a more efficient series of transition cycles to accomplish cache address invalidations both during a cache hit or a cache miss cycle, the present architecture and methodology permits a faster cycle of cache address invalidations when required and also permits a higher frequency of processor access to cache without the processor being completely locked out from cache memory access during heavy traffic and high level of cache invalidation conditions.