Abstract: A system for laying out a capacitor array (400) implements a programmable capacitor (33-39) whose operation is controlled with a binary control word. A programmable capacitance is produced by coupling binary weighted, switchable capacitors (101-107) between terminals (51, 52) of the programmable capacitor. The capacitor array includes two or more unit capacitors (101, 103) of unequal areas. The other capacitors in the array are derived by interconnecting multiple capacitors that match one of the unit capacitors. Die area is reduced while accuracy is maintained by controlling the larger unit capacitor with the least significant bit of the binary control word whenever possible and using the smaller unit capacitor only as a trim capacitor.

Abstract: A power semiconductor device (10) and a method for increasing the turn-on time of the power semiconductor device (10). The power semiconductor device (10) has a first stage (13) and a second stage (14), where the transconductance of the first stage (13) is less than the transconductance of the second stage (14). The turn-on time of the power semiconductor device (10) is increased by turning on the first stage (13) before turning on the second stage (14).

Abstract: A circuit and method control the common-mode potential at an output (17, 18) of a fully differential amplifier (32) by feeding forward a common-mode correction signal through the amplifier. An input signal (V.sub.IN+ -V.sub.IN-) is amplified in the amplifier to produce a differential output signal (V.sub.O- -V.sub.O+) at the output. A common potential of the differential inputs (37, 38) of the amplifier is sensed with a transistor (54, 56) biased to a reference voltage (V.sub.CM) and amplified through the amplifier to produce a common-mode correction signal to offset a common-mode component of the differential output signal. A feedback circuit (33-36) is used to develop the common potential from the common-mode component.

Abstract: A Magnetoresistive Random Access Memory (MRAM) device (10) and a method for manufacturing the MRAM device (10). The MRAM device (10) has a plurality of pairs of sense lines (21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B), a plurality of pairs of memory cells (51A, 51B), and a plurality of word lines (31, 32, 33, 34). For two adjacent sense lines (21A, 22A), a first end of the first sense line (21A) is placed adjacent to a second end of the second sense line (22A) and a second end of the first sense line (21A) is placed adjacent to a first end of the second sense line (22A). Decoding transistors (82, 83, 84, 85, 86, 87, 88, 89) are connected to the second ends of the plurality of pairs of sense lines (21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B).

Abstract: A comparator (12) and method compare first and second signals (V.sub.IN+, V.sub.IN-) to provide an output signal (V.sub.O, V.sub.OB). A transistor (43) couples a supply terminal (64, 66) of the comparator to a power supply (V.sub.DD) to enable the comparator for comparing the first and second signals. When the output signal is valid, it turns off the transistor to isolates the supply terminal from the power supply. As a result, power is reduced and a change in the first and second signals is prevented from changing the output signal. When the transistor turns off, a charge is trapped on the supply terminal that unbalances the comparator and causes a comparison error. A balanced condition is restored with a discharge circuit (31-33) coupled to the supply terminal to alter the charge when a control signal (RESET) is applied.

Abstract: A circuit for controlling current flow (I.sub.COIL) through a coil of an electromechanical device (101) uses a first timer (118) to measure the pulse width of a first drive pulse (22) and to store a proportional first value at an output (121). A second timer (124) receives the first value and generates a second value less than the first value to represent a time interval shorter than the pulse width of the first drive pulse. The second timer initiates the time interval with a second drive pulse (24) and provides a sampling signal (V.sub.SAMPLE) as the time interval terminates to sense an average current flow through the coil before the second drive pulse terminates.