Abstract: A computer system comprising a central processing unit (CPU) configured to accept coordinate type data from a touchpad or the like. The CPU has an operating system executing thereon with special support for interfacing to the touchpad. The operating system has the following capabilities: (1) mapping out geometric regions of the touchpad and assign the regions to specific region identifiers responsive to application programs and (2) determining the region identifier of a touched region and passing that region identifier to the application program. Support is also provided for changing the units of the commands used to define the regions.

Abstract: An information processing system which has (a) a CPU that is operated in a normal mode during which the CPU is driven at a relatively fast operating clock rate, and a power saving mode during which the operating clock has a lower rate or is halted; (b) at least one peripheral device; (c) a bus for performing communication between the CPU and the peripheral device; (d) a termination detector detecting a completion of a predetermined transaction between the CPU and the peripheral device; (e) a time counter measuring a predetermined period of time after the completion of the predetermined transaction; and (f) a power saving control causing the CPU enter the power saving mode until the time counted by the time counting means reaches the predetermined period of time.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor has, on a single VLSI device, a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors, and further has registers for controlling access, and the modes of access, to data held in memory.

Abstract: Disclosed is a computer system that includes a CPU that can be operated both in a normal mode and in a power saving mode. The system further includes at least one peripheral device and a bus for allowing communication between the CPU and the peripheral device. A bus cycle detector monitors a bus cycle on the bus and a condition determiner determines the operation mode for the CPU in a specific bus cycle that is detected by the bus cycle detector. A signal generator is used to provide to the CPU, a control signal for changing the CPU's operation mode in accordance with a determination result obtained by the condition determiner. The disclosed system can reduce the operating frequency of a CPU or halt the operation of the CPU in accordance with an appropriate timing even when asynchronous communication is performed with peripheral devices.

Abstract: In a data processing system, an object is displayed on a display coupled to the data processing system. Also displayed, is a multiple-point cursor having at least first and second pointing spots. The multiple-point cursor is typically positioned by user manipulation of a pointing device, such as a mouse. In response to a user indication, such as a mouse click, a first operation is performed on the displayed object if the first pointing spot is positioned over the object during the mouse click. Similarly, a second operation is performed on the displayed object in response to a user indication while the second pointing spot of the multiple-point cursor is positioned over the object on the display. Such first and second operations may include a copy operation and a move operation.

Abstract: Disclosed is a docking unit which includes a mechanical lock having an unlock position and a lock position. A security key is provided for manipulating the mechanical lock to move between the unlock position and the lock position. The security key is (1) detachable from the mechanical lock at the lock position and (2) undetachable from the mechanical lock at the unlock position. The docking unit further includes a latch for securing a portable computer to the unit in response to positioning of the mechanical lock in the lock position and releasing the computer from the unit in response to positioning of the mechanical lock in the unlock position. The unit also includes an inhibitor for selectively inhibiting the mechanical lock from movement to the lock position.

Abstract: An aseismic support structure which includes a fixed part which is attached to a stationary floor, an equipment connection part for holding part of the equipment and a moving part coupled to the fixed part and the equipment connection part and wherein the moving part is freely movable relative to the fixed part in any direction parallel with the stationary floor and the equipment connection part is freely rotatable about the moving part. The equipment can have a caster which is held by the equipment connection part. For a weak earthquake shock, a caster lock portion of the equipment connection part locks the caster of the equipment to prevent the movement of the equipment. For a stronger earthquake, resonance is prevented by the moving part moving in a direction parallel with the stationary floor, and for a ruinous earthquake the vibration of the moving part is absorbed by a shock absorbing member attached to the fixed part.

Abstract: A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Most audio and/or video compression algorithms use a Huffman style bit compression scheme with compression codes in variable length bit fields. The compressed data is a compacted bit stream which must be interpreted serially in order to extract the codes. In contrast to most microprocessors which process bit streams only inefficiently, the present invention uses a serialization FIFO to provide a hardware assist to the Huffman encoding/decoding.

Abstract: Disclosed is a computer system which can be powered on by at least a first and a second method wherein the first method is different from the second method. The computer system is operative to allow a user to select which one of at least two different pre-selected ordered lists of initial program load (IPL) devices are to be used depending on whether the system was powered on by the first method or the second method. The system includes a processor coupled to a local bus and an input/output (IO) bus. A non-volatile memory is coupled to the processor and the IO bus. The non-volatile memory has a basic input output system (BIOS) stored therein and the BIOS is effective for responding to the energization of the computer system by initiating a power on self test (POST). The non-volatile memory also stores a first pre-selected ordered list of IPL devices and a second pre-selected ordered list of IPL devices.

Abstract: An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.

Abstract: Disclosed is an electronic apparatus which includes a power supply unit and a constant voltage rechargeable battery. The power supply unit activates a dedicated charging circuit, which is located near the battery, only at the charging end stage after the terminal voltage of the battery has attained a predetermined value, and provides constant voltage control for a charge current by using the charging circuit. The charging circuit, however, is not employed at the initial charging stage, where precise constant voltage control is not required. The output current, for which constant current control is performed by the AC adaptor, is employed unchanged as a charge current, with which quick charging is performed. That is, since a transformer in the charging circuit is not activated at the initial charging stage, a power loss, which accompanies the operation of the transformer, and heat generation and the occurrence of magnetic noise in the electronic apparatus can be reduced to a minimum.

Abstract: Disclosed is an aseismic support structure having one end secured to a fixed floor and another end connected to a subject structure placed on a floating floor. The aseismic support structure includes a toggle bar, an attachment section and a mounting section. The toggle bar has a universal joint at each end and is adjustable in its length to have a predetermined length. The universal joints are rotatable around axes in the horizontal and vertical directions, respectively. The attachment section is connected to the toggle bar through one of the universal joints, and has at another end a third universal joint comprising a vertical rotation section. A cantilever extends substantially parallel to the fixed floor, is connected to the attachment section by the third universal joint at one end and has a fourth universal joint at another end. The mounting section is connected to the cantilever by the fourth universal joint and secures the equipment.

Abstract: Disclosed is a method and apparatus for processing two analog composite video signals to be displayed to a human observer. The system includes at least a first and a second video source for generating first and second analog composite video signals respectively, and a selector coupled to the first and second video sources. The selector is operative to supply either the first or second analog composite video signal to one input of a video processor and independently and simultaneously supply either the first or second analog composite video signal to a second input of the video processor. The video processor is operative under control of a CPU to generate an output analog composite video signal comprised of a portion of the analog composite video signal supplied to the video processor's first input and a portion of the analog composite video signal supplied to the video processor's second input.

Abstract: Disclosed is a video game system for connecting to the Internet and allowing a user to transfer/receive data therefrom. The video game system includes a connector port for removably and electrically connecting a cartridge to the game console. The cartridge includes an application program stored therein, a modem and a telephone port for transferring data between the Internet and the video game system via a telephone line. A processor is electrically coupled to a system memory, the connector port and the I/O port. The processor is operative to (1) transfer the application program from the first cartridge to the system memory, execute the application program out of system memory and display an Internet graphical user interface (GUI) on the video display device and (2) execute Internet protocol programs to connect to the Internet and transfer data between the Internet and the video game system via the graphical user interface.

Abstract: Described is an extension device for use with a computer system which includes a memory for storing an application program which can perform at least one software function. A modem is operative to encode the at least one software function to first tone signals and transfer them onto a telephone line. The modem is further operative to decode second tone signals received from the telephone line and transfer the first tone signals in response thereto. The system includes power management circuitry (PMC) for changing the system from a low power state to a normal operating state responsive to a wake up control tone signal. The extension device includes a keypad for inputting (1) command signals corresponding to the at least one software function and (2) a wake up command signal. A display is included on the extension device for displaying information related to the at least one software function. The extension device also includes a controller coupled to a signal generator and a signal decoder.

Abstract: A method and system are disclosed for simulating a direct memory access (DMA) function to access memory in a host computer having a DMA controller for the purpose of enabling the transfer of data between the host memory and a computer accessory data handling device not capable of DMA operation. The accessory data handling device can be operably connected to the host. The address contents of the DMA controller can be read to determine the location in the host memory where data is to be transferred from the host memory to the accessory data handling device or from the accessory data handling device to the host memory. Data is read from the host memory at the address specified in the DMA controller and written to the accessory data handling device or read from the accessory data handling device and written to the host memory at the address specified by the DMA controller, respectively.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. A single VLSI device has a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, and the processors are joined together by a wide data bus formed on the same substrate as the processors. Each processor has a load/store unit, a translation unit associated with the load/store unit, and an index control register for controlling any translation of data bit streams passed through the load/store unit.