Abstract: Defines and handles segments in messages to place pauses and interruptions within the communication of a message between transmitted segments of the message. A common link switch is used in a network to connect links to all nodes, the segment structures in each message is preserved when packets of each message are passed within the switch to a switch transmitter connected to the destination node indicated in each packet of the message for transmitting each of the message segments. Each transmitter stores the source identifier of the first packet it transmits for a segment and then gives priority to transmitting packets which contain source and destination identifiers which match the current transmitter stored source identifier and match the destination node connected to the transmitter. This priority enables each switch transmitter to interleaves segments of concurrent messages while preserving the segmentation of transmitted packets to maintaining a maximum network communication rate for the messages.

Abstract: Enables a processor to quickly recover reliable use of a multi-cycle index used in a branch prediction mechanism for certain types of flush events occurring in the processor pipeline, whether the flush event occurs for a non-branch instruction or for a branch instruction contained in the same dispatch group. A GHV (global history vector) value is used in the generation of a multi-cycle index required for locating a prediction in a GBHT (global branch history table) for the instruction associated with the GHV value. The GHV value is captured in a BIQ (branch information queue) element representing each branch instruction selected for execution of a program. The BIQ element also captures an associated GHV count when the GHV value is captured.

Abstract: A novel structure for a highly-scaleable high-performance shared-memory computer system having simplified manufacturability. The computer system contains a repetition of system cells, in which each cell is comprised of a processor chip and a memory subset (having memory chips such as DRAMs or SRAMs) connected to the processor chip by a local memory bus. A unique type of intra-nodal busing connects each system cell in each node to each other cell in the same node. The memory subsets in the different cells need not have equal sizes, and the different nodes need not have the same number of cells. Each node has a nodal cache, a nodal directory and nodal electronic switches to manage all transfers and data coherence among all cells in the same node and in different nodes. The collection of all memory subsets in the computer system comprises the system shared memory, in which data stored in any memory subset is accessible to the processors on the other processor chips in the system.

Abstract: An aligned Instruction cache (AIC) containing multiple instruction cache sectors in which may be recorded out-of-sequence blocks of instructions. Basic blocks of instructions are aligned in AIC sectors at program run time. An AIC directory uses the current instruction address to select an AIC directory entry and an associated row in the AIC containing multiple sectors. The AIC directory entry contains multiple “Sector S first address” fields respectively associated with the multiple AIC sectors, each of these directory fields containing the address of the first instruction in the associated AIC sector S when its contents are valid. A “fetch history table” (FHT) contains four FHT entries for each associated AIC row organized in FHT sets of four entries. Each valid FHT entry records a predicted sequence of instructions based on a prior actual execution of the sequence in the same program, which may repeat over and over again.

Abstract: A method and system for providing a user interface in a data processing system to be utilized for performing a plurality of tasks on a plurality of diverse central processing complexes, wherein processes utilized to perform the plurality of tasks are transparent to a user, and wherein the user interface utilized to perform the plurality of tasks is common across diverse central processor complexes. A library containing interface parameters for each central processing complex is established. The interface parameters include information necessary to tailor the user interface for the specific target central processing complex, as well as processes for performing selected tasks within each of the central processing complexes. The user is prompted to select a task for at least one of the diverse central processing complexes. At least one interface parameter from the library of interface parameters is selected in response to the user selecting a task for at least one of the diverse central processing complexes.

Abstract: Six instructions for the manipulation of discontinuous memory locations in a computer memory are described. They are: Compare and Load (CL), Compare and Swap (CS), Double Compare and Swap (DCS), Compare and Swap and Store (CSST), Compare and Swap and Double Store (CSDST), and Compare and Swap and Triple Store (CSTST). In each instruction a processor associates a programming-specified blocking symbol with a lock not accessible to software. The lock is used by any of these instructions only during its single instance of instruction execution, and the lock is made available (unlocked) at the end of each instance to then enable another blocking-symbol instruction instance to use the lock, thereby serializing concurrent multiple processor requests for accessing the same resource. Programming associates resources in a system with the unique blocking symbols. Each instance of these instructions executes an operand earlier prepared from a data value taken from the resource..

Abstract: Preprocessing emulation methods utilizing search argument controls for a template routine address table in a target computing system. Target routines are stored in a target computing system for emulating incompatible instructions of an incompatible architecture which need not be recognized by the architecture of the target computing system. Preprocessing of template routines is preferrably executed on an Auxiliary Emulation Processor (AEP) which may access and patch (modify) some or all of the target instructions in any selected target routine and send them through a queue to a target processor for execution. Execution of the target routines on a target processor emulates the execution of incompatible instructions in an incompatible program in the incompatible architecture.

Abstract: Provides a program translation and execution method which stores target routines (for execution by a target processor) corresponding to incompatible instructions, interruptions and authorizations of an incompatible program written for execution on another computer system built to a computer architecture incompatible with the architecture of the target processor's computer system. The disclosed process allows the target processor to emulate incompatible acts expected in the operation of an incompatible program when the target processor itself is incapable of performing the emulated acts. Each of the instructions, interruptions and authorizations found in the incompatible programs has one or more corresponding target routines, any of which may need to be preprocessed before it can precisely emulate the execution results required by the incompatible architecture.

Abstract: Speeds up a commanded system to read or write data for a large number of data frames transmitted on a link by executing a TRANSFER STRUCTURE instruction that automatically controls the reading or writing of a large number of scattered storage blocks in the storage of the commanded system containing, or to contain, the data transmitted on the link.

Abstract: The present invention significantly reduces or eliminates the involvment of central processors in the message block handling of received communication-link responses within a Central Processing Complex (CPC). When a commanding system sends a command, it must receive a response frame from the commanded system indicating if the command was correctly received or not. A significant amount of time is required for the commanding system processor to move the received response frame from a receiving link buffer to an area in the CPC memory. The preferred embodiment avoids the need for having a commanding system processor either wait for or be interrupted to handle the response frame. The preferred embodiment provides advanced preparation of a data mover in a manner to enable the data mover in the computer system to handle the reception of each response frame without involving the commanding system processor.

Abstract: Apparatus for protecting memory storage blocks (page frames) against unwanted I/O accesses, including I/O data transferred in an unwanted direction. I/O storage keys are provided in an I/O protection array. Each I/O key is comprised of one or two bits and is associated with a respective storage block in computer memory. If the array contains two bit I/O keys, each key has 4 settings for controlling I/O accesses to an associated storage block; which: 1) inhibit an I/O access in the input direction of I/O data flow, 2) inhibit an I/O access in the output direction of I/O data flow, 3) allow I/O accesses in both directions, or 4) prevent all I/O accesses. If the array contains single bit I/O storage keys, each key has two settings, which: 1) prevent all I/O accesses in the associated storage block, or 2) allow all I/O accesses in the associated block. No I/O program keys are needed for controlling this type of I/O protection, which avoids key comparison operations by the I/O access protection apparatus.

Abstract: Provides a processor method of executing instances of a Perform Locked Operation (PLO) instruction for enabling a recovery of the consistency of a resource unit being changed by a PLO instance when processor failure occurs anywhere during execution of the PLO instance. The method uses a PLO save area for each processor in a computer system capable of executing PLO instructions. Each PLO save area has a resource-inconsistency (RI) indicator having an RI state and a non-RI state, and stores the function code (FC) of the PLO instance. The RI state indicates that the resource is in a non-usable potentially inconsistent state, and the non-RI state indicates the resource is in the consistent state and may be used. A processor executing a PLO instance writes into its PLO save area all resource addresses where a change is to be made in the resource unit, and also writes in its PLO save area all operand values which will be used to change the resource at the associated addresses.

Abstract: Missing interrupt handler (MIH) software features for supporting a variable MIH timeout for I/O requests issued by an operating system (OS). The MIH timeout is varied to prevent a false indication of a failure in an I/O device operation, which is indicated if the MIH timeout occurs. By extending the MIH timeout, the I/O device is given more time to complete its operation, and the extension is provided when the device control unit (CU), or the OS, determines an I/O operation cannot complete before the shortest available MIH timeout. The length of a primary MIH timeout period is extended to a secondary MIH timeout period in response to the OS detecting that an I/O request has a long command that requires a long operating time in the I/O device, or a signal from the device's CU indicating that the current operation in the I/O device is taking an excessive time without the device being in any error condition.

Abstract: PLO (perform locked operation) instructions containing blocking symbols are executed on each of multiple processors in a computer system to control coherence in data structures which may be changed by any of multiple processors in a computer system. The blocking symbol is extracted from a PLO instruction instance when invoked by its executing processor. Then the processor hashes the blocking symbol using hardware-microcode (H-M) to generate the location of a lock field in protected storage. The PLO instruction's blocking symbol is associated with a computer resource unit by software providing the PLO instruction, and the blocking symbol then associates the resource with a protected lock through the hashing operation on the blocking symbol. A processor must obtain the lock for a blocking symbol before the executing PLO instruction instance is allowed to make access and change the resource unit associated with the blocking symbol.

Abstract: Two or more user applications executing on one or more processors, each controlled by an operating system, share use of a list and subsidiary list structure within a Structured External Storage (SES) facility to which each processor is connected. One of the applications registers interest in particular state transitions affecting one or more subsidiary lists within the list structure, causing a process within the SES to notify the appropriate processor when a list operation causes the particular state transition, without interrupting processing on the processor. The application receives notice of the state transition by periodically polling a vector within the processor, or by receiving control when a test by the operating system of a summary indicator for the vector causes an application exit to be driven.

Abstract: Provides within a semiconductor chip a plurality of internal DRAM arrays connected to each section data bus. A cross-point switch simultaneously connects the plural section data buses to a corresponding plurality of port registers that transfer data between a plurality of ports (I/O pins) on the chip and the section data buses in parallel in either data direction to effectively support a high multi-port data rate to/from the memory chip. For any section, the data may be transferred entirely in parallel between the associated port and a corresponding port register, or the data may be multiplexed between each port and its port register in plural sets of parallel bits. Each of the DRAM banks in the chip is addressed and accessed in parallel with the other DRAM banks through a bank address control in the chip which receives all address requests from four processors in a computer system.

Abstract: A testing apparatus designed to check the completion of a command issued earlier in a multiprocessing system having a plurality of nodes. During an initialization phase, each command has been identified by a handle and a record containing the task to be performed asynchronously had been established. When a request for checking the completion of a command is issued, the pre-established record is simply checked for location of last task executed and completed. If the last or most current task is not the last task before the completion of the total command, the user application can choose to either continue the operation of command processing or permanently or temporarily abandon it.

Abstract: A pluggable connector capable of connecting a large number of electrical transmission lines per connector, and small enough to enable a large number of connectors to be added to a multi-chip module. For example, 5 or 6 of these connectors can add over a hundred coaxial cables to a module. Improved I/O communications is added to a module by such coaxial cables, since they can communicate very high frequency signals in noise prone environments. The pluggable connector is embedded in a multilayer module (e.g. ceramic or glass) for conveying digital information to transmission lines internal or printed on the surface of a module. Each connector contains a receptacle 19 having a silicon contact structure embedded in an edge of a multi-chip module. The contact structure is formed with a plug-receiving angle for deflecting multiple cantilevered plug contacts 17 into engagement with corresponding receptacle contacts 22.

Abstract: For high-speed single-ended sensing of the small signal delivered from a (static) RAM or ROM cell, a voltage dependent timing delay circuit is disclosed which prevents early triggering of the set signal of the sense amplifier (SSA 66) when applying a high voltage screen test (i.e. 1.5 times V.sub.DD) to the cell. The timing of the SSA signal is achieved by a high precision delay chain comprising inverters, which is loaded by a voltage dependent current sink (70) coupled to the output of the chain. The inverter delay chain controls the input (SE0) for a driver for the SSA line (66). The current sink may be a pull down NFET (70) which is only activated when the supply voltage is above a determined switching threshold therefor. The gate voltage of the NFET is controlled by a bias control circuit (72) in such a manner that during operation at typical voltage levels, the NFET is deactivated, whereas at higher operating voltage levels (such as 1.5 * V.sub.

Abstract: Missing interrupt handler (MIH) internal software features support a variable MIH timeout for I/O requests issued by an operating system (OS), when the same OS is involved with both an executing I/O request and a waiting I/O request. The OS varies its MIH timeout period without a signal from any I/O entity to prevent a false indication of a potential failure in a current I/O device operation. If a current I/O request has not completed when the OS senses the end of a primary MIH timeout period, started when issuing that request, the OS then scans the I/O program of that I/O request for any contained long-running command. (Most I/O requests complete during their primary MIH timeout period.) If a long command is found, the OS extends the MIH timeout period from the primary MIH timeout period to a long MIH timeout period, The latter gives the I/O device more time to complete its operation before the OS indicates it has a potential I/O error condition.