Abstract: A method for acquiring the node identifier of a node in a data processing input/output (I/O) system having a plurality of nodes. This procedure is part of the initialization of each node in the I/O system and may be used to establish the configuration of the I/O system such that if a connection breaks or a fault occurs between nodes, the configuration can be confirmed after the break or fault is corrected. This prevents data from being sent to the wrong device if lines were connected in a different configuration during the correction of a fault. The node identifier is a worldwide-unique identifier such that only one node is identified by a node identifier. The node identifier contains a validity code that specifies if the node identifier is valid. Also disclosed is a retry procedure for retrying the acquisition of a node identifier if the acquired node identifier is not valid, and a deferral procedure which defers the retry procedure if a link is not available.

Abstract: A Branch in Subspace Group (BSG) instruction is executed in problem state (for example by an application program) for providing a fast instruction branch between address spaces within a restricted group of address spaces called a subspace group. The subspace group contains two types of address spaces: a base space and any number of subspaces. The subspace group is set up in a control table associated with each dispatchable unit (DU). This DU control table contains: an identifier of a base space, an identifier of an access list that contains identifiers of all subspaces in the subspace group, an indicator of whether CPU control was last given to a subspace or to the base space, and an identifier of a last entered subspace in the group. The BSG instruction has an operand defining a general register containing the target virtual address and an associated access register containing an access-list-entry token (ALET) defining the target address space.

Abstract: A method for reducing fetch time in a computer system provides a memory fetch cycle that is shorter than the memory store cycle. Each chip of the computer system has at least one dynamic random access memory array (DRAM) and a small high speed cache static random access memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and recovery in the DRAM. The RAS starts DRAM recovery for a fetch cycle at or near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that control DRAM recovery while fetching during DRAM data from the SRAMs, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.

Abstract: A matrix of cluster connectors for switching and interconnecting large numbers of optical fiber and/or electrical conductors (such as coaxial lines) to a module used in computers, communications and related applications. The matrix of pluggable cluster connector receptacles is located on a major surface of a module, such as a ceramic multi-chip module or a thin film silicon chip carrier module. A semiconductor wafer is fabricated with a matrix of angled slots fabricated to form the matrix of receptacles. The wafer is a major surface of the module, and may have another opening for chips fastened to the module surface below the wafer. Each angled slot engages an end of a plug member to align any optical fiber ends contained in the cluster held by the plug with a corresponding lens/light signal transducer in the module.

Abstract: Obtains a large increase in the number of fiber optic inputs/output (I/O) lines connectable to a module by enabling edge connection of multiple clusters of optical fibers to be connected around a module. Each connector connects a cluster of optical fibers in a small dimension of space on the module. Many distinct pluggable connectors may be provided along one or more edges of a module. The optical-fiber cluster connectors are embedded in indentations around the edges of a multilayer glass/ceramic (MLGC) multi-chip module (MCM), which may be a thermal conduction module (TCM), containing an integrated photonic receiver and/or transmitter for each fiber. Each connector supports a large number of fibers from a single cable, and a large number of connectors may be provided in a single module. Easy plugging and unplugging is obtained for each connector without interferring with any existing cooling apparatus or I/O pins of the module.

Abstract: A method of transmitting compressed data using a Ziv-Lempel compression/expansion algorithm, using an adaptive Ziv-Lempel (AZL) dictionary modified to a mature state. The mature state is signaled by a time to freeze signal sent as a switch-over signal from a transmitting location to each receiving location. These signals freeze and synchronize the AZL dictionaries at both locations, and starts a translation of the frozen AZL dictionary to a static SZL dictionary--at least at the transmitting location. The SZL dictionary is then used to compress records being transmitted. An index translation process is generates translation information to allow the receiving locations to decompress SZL indices into original characters. The AZL-to-SZL dictionary translation process re-organizes the frozen AZL to an SZL dictionary. The SZL process is used until either the end of the inputted sequence, or a time to unfreeze signal is generated.

Abstract: A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.

Abstract: An apparatus and method are established for recognizing guest virtual machines which require only a subset of interpretive execution facilities. The interpretive execution initialization process recognizes subset candidates and bypasses initialization of those facilities not required by the candidates. The candidates are typically short duration jobs and a reduction of initialization and termination overhead creates a substantial performance improvement. The translation lookaside buffer operation is modified to flag subset guest entries as host entries and to associate a unique segment table origin with each subset guest. This allows the TLB entries to remain between guest machine dispatches eliminating TLB purge time and allowing potential reuse of TLB entries if the same guest is repeatedly dispatched within a short time period. The guest machine state description is modified to flag subset candidates based on address translation and timing requirements.

Abstract: A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machine, or an underlying guest machine. A system for reducing the number of cases in which guest translations are based on host page table entries is provided. Additional logic is supplied to analyze each invalidate page table entry (IPTE) instruction to minimize the extent of purging required as a result of that instruction. When the region relocate facility is in operation, or when no pageable TLB's have been constructed, only the entry corresponding to the page table entry to be invalidated need be purged. This limited purging reduces the overhead by reducing the time spent in purging and the time required in address translation to rebuild the TLB.

Abstract: Enables the flexible handling of time, iteration and resource type as variables. For example, project/process simulation tool defines an activity; defines alternative resources required to commence the activity; determine availability of the alternative resources; and varies a duration of the activity based on the availability of the alternative resources. According to another aspect, a modelling process is a computer, provided for including: supplying a modeling program having a plurality of predefined stages of execution which collectively define a transfer function of an activity within a network; defining a plurality of user supplied programming statements, each provided with a label indicative of at least one of the stages of execution; and, causing the modeling program, to execute the user supplied programming statements, each immediately followed by a stage of execution indicated by the associated label.

Abstract: A computer partitioner provides services to several partitions coexisting in a computer at one time. To operate efficiently, certain applications executing within a partition will intermittently require specific services to be delivered to them in a timely fashion. This disclosure provides a mechanism for a computer partitioner to provide special time dependent services to partitions on a dynamic demand basis.

Abstract: A tree sorter having hardware logic node registers and output selectors plus comparators enables a vector processor to perform sort and merge operations. A system and method of providing one output record each cycle provides performance enhancement over similar scalar operation. Storage to storage traffic is drastically reduced because the hardware tree and update logic is implemented in the Vector Processor. Vector registers provide input data to the hardware tree structure. Output records sorted by key together with address ID are placed in storage. Multiple Vector count and multiple Vector Interruption Index (VIX) operation, string length and merge masks are used in conjunction with a vector merge instruction. The data input record key field has both long and short formats. Actual key data or codewords may be used. The vector merge forms a new codeword when compare equal codewords are encountered.

Abstract: A mechanism for an automated system to allow a user of the system to demonstrate his legitimacy by demonstration of secret knowledge. The mechanism is resistant to compromise by observation of its use. An array of symbols is presented to the user and the user is required to manipulate several symbols at once until assigned key symbols are manipulated into predetermined states. Doing so effectively prevents an observer from determining which symbols are the ones of interest. For example, pushing a button might cause several symbols in the array to exchange their positions. The user continues to do this, having, perhaps, to use several different buttons, until a certain subset of the symbols appears in certain locations within the array. (In this example, the arrangement of this subset of symbols is the user's password or PIN.

Abstract: A method of automatically invoking a recoverable and fault tolerant implementation of the complemented/recomplemented (C/R) error correction method without the assistance of a service processor when an excessive error is detected in main storage (MS) by ECC logic circuits. An excessive error is not correctable by the ECC. These novel changes to the C/R method increase its effectiveness and protect the C/R hardware against random failure. Further, if an excessive error is corrected in a page in MS, an excessive error reporting process is provided for controlling the reporting using a storage map to determine if a previous correction in that page has been reported. If it has been reported, then no further reporting of soft excessive errors is made for that page. A service processor is signaled in parallel to update its persistent copy of the storage map so that on a next initializations of MS the memory map can be restored in the memory.

Abstract: Provides a method for measuring the busy utilization time for I/O channel used by any of plural operating systems (OSs) in a CEC. The measured utilization time for any OS excludes the time shared channels are utilized by other OSs during a measurement period. A channel measurement facility (CMF) is provided in the I/O subsystem hardware and microcode for each of the OSs in the I/O subsystem. The CMF is logically constructed because it uses only a small portion of I/O resources already existing in a CEC by adding microcode to control these resources to perform the time measurement function. The resources for a logical CMF including the partial use of: an I/O processor to store identifiers of an assigned OS, the partial use of channel processors controlling channels selected by the assigned OS during a measurement period, the local storage of each I/O processor, and OS storage needed for communicating the measurement data from the CMF to the OS.

Abstract: A coherence directory and its methods of operation are disclosed for private processor caches in a multiple processor system to control data coherence in the system. It provides cross-invalidate (XI) controls for the assignment of exclusive and public ownership to data units in the processor caches, including required cross-invalidation of data units among the processor caches to obtain data coherence in the system in an efficient manner. The coherence directory can be used in a multiple processor system with or without any shared second level (L2) cache, shared or private. When a shared L2 cache is used to improve system access time, the coherence directory can also be used as the second level directory for the shared L2 cache and eliminate the need for any additional L2 directory(s).

Abstract: In a tightly coupled multiprocessor system, I/O interrupts are distributed to respective processors in accordance with load conditions of the processors without partiality to any one processor. Interrupt arbitration circuits provided in respective processors receive an interrupt request from an I/O device, effect interrupt arbitration using a parameter indicating the load condition of each processor as a first interrupt priority. If the arbitration fails to determine a sole processor, additional arbitration finally selects a sole processor P on the basis of the second interrupt priority which is varied circularly.

Abstract: A single non-privileged instruction copies a page of data from a source virtual address in an electronic medium to a destination virtual address in the same or in a different electronic storage medium, and without the intervention of any supervisory program when each medium and the virtual addresses are previously determined. The instruction is not required to specify which medium it will use, does not require its user to know what backing medium it will access, does not require main storage (MS) to be its backing medium, and allows different types of physical addressing to be used by different media. The instruction can lock any page for use in a multi-processor (MP). No physical direction of data movement is provided within the non-privileged machine instruction, which only designates virtual direction of movement. The separation of virtual direction from physical direction is done by avoiding instruction control over selection of electronic media.

Abstract: An alternate instruction architecture which uses the preexisting dataflow and hardware controlled execution units of an otherwise conventional pipelined processor to accomplish complex functions. Additional hardware controlled instructions (private milli-mode only instructions) are added to provide control functions or to improve performance. These milli-mode instructions augment the standard "user visible" architected instruction set (which in the preferred embodiment is the System 390 instruction set). Millicode routines can intermingle the milli-mode only instructions with standard system instructions to implement complex functions. The set of instructions available in milli-mode can be considered to be an alternate architecture that the processor can execute. The millicode and standard system architectures each have there own set of architected registers. However, these registers are dynamically taken from and returned to a common physical register pool under control of a register management system.

Abstract: A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.