Abstract: The present invention provides a programmable modular circuit for testing and controlling a system-on-a-chip integrated circuit, and applications thereof. In an embodiment, the programmable modular circuit comprises a plurality of serial-to-parallel interface registers coupled together by a data line, a clock line, and an enable line. Each of the plurality of serial-to-parallel interface registers is coupled to a module of the system-on-a-chip. The data line and the clock line are used to serially clock data into the plurality of serial-to-parallel interface registers. Applying a first logical value to the enable line provides the data serially clocked into the plurality of serial-to-parallel interface registers to modules of the system-on-a-chip. Applying a second logical value to the enable line provides default values to modules of the system-on-a-chip.

Abstract: A method of processing a signal in a wireless network including multiple chains is provided. This method can include receiving the signal in a receiver and, for each chain, performing a Barker correlation on the signal to generate a Barker correlated signal. At this point, an autocorrelation can be performed on the Barker correlated signal to generate an autocorrelated signal. The autocorrelated signals from the multiple chains can be summed to generate a summed output. Additional processing, e.g. at least one of CCK weak signal detection, peak selection in a rake receiver, frequency estimation, and differential decoding, can then be performed based on the summed output.

Abstract: An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve.

Abstract: A detailed placement process which optimizes cell placement with up to one hundred percent densities in a linear run time. The output from a conjugate-gradient coarse placement process is input to the detailed placement process. A dynamic programming technique is used to optimize cell placement by swapping cells between two or more rows. The search space is pruned beforehand. A greedy cleanup phase using an incremental row placer is used. Thereby, the detailed placement process handles congestion driven placements characterized by non-uniform densities expeditiously and efficiently.

Abstract: A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D? signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45?±10%) in the USB transceiver.

Abstract: A concrete lid for an in-ground utilities box includes a plastic reinforcement structure filled with concrete. The plastic reinforcement structure includes one or more plastic sidewalls that protect the edges of the lid from damage. The upper and lower surfaces of the lid are exposed concrete (with the exception of the upper and lower edges of the one or more plastic sidewalls). The one or more plastic sidewalls laterally surround a plastic reinforcement grid, which is centrally located between the upper and lower edges of the one or more plastic sidewalls. The one or more plastic sidewalls can be integrally formed with the plastic reinforcement grid. The plastic reinforcement grid reinforces the concrete lid, eliminating the need for separate reinforcement material. Support struts can be used to support the plastic reinforcement grid while wet concrete is being poured into the plastic reinforcing structure.

Abstract: A method and apparatus in a multiple sub-carrier digital communication receiver that estimates a communication channel. A second set of channel estimates are generated based on a Wiener filter interpolation of a first set of channel estimates. Pre-determined transmit pilot symbols may be used to generate the first set of channel estimates in an OFDM communication system. The coefficients of the Wiener interpolation filter are based on a channel impulse response estimate that includes two or more narrow regions of non-zero amplitude separated by one or more wide regions of essentially zero amplitude. The Wiener interpolation filter coefficients are also based on a Doppler frequency estimate. The Doppler frequency estimate may be determined from the first set of channel estimates, while the Wiener interpolation filter coefficients may be generated from a pre-determined set of channel impulse responses.

Abstract: The present invention discloses a mixer comprising with an input stage (100) for receiving and amplifying input signals (VINP, VINN) and an output stage (300) for outputting output signals (Voutp, Voutn). A switching stage (200) is coupled between the input stage (100) and the output stage (300), the switching stage (200) mixing the amplified input signals with a local oscillator signal (vlop, vlon) to produce the output signals (Voutp, Voutn) at the output stage (300). An RC circuit (cop, rop; con, ron) is connected to the output stage (300) and adapted to move the pole of the output signals.

Abstract: A method to equalize multiple-input multiple-output (MIMO) signals assigns a weight to the output of each receive chain in the MIMO system based on a first noise power value in each receive chain. A second noise power value can be computed using a difference between identical symbols from one or more weighted/un-weighted receive chain signals. Notably, the second noise power value includes thermal noise, phase noise, quantization noise, and distortion noise. The weighted outputs of the receive chains and the second noise power estimate may be used in an equalization calculation to recover the input signal.

Abstract: A method of providing simulation results includes detecting any power net and rail in a circuit netlist. The circuit can be divided into net-partitioned blocks. Using these net-partitioned blocks, a topological analysis can be performed to identify cuttable/un-cuttable devices and synchronization requirements. Then, the circuit can be re-divided into rail-partitioned blocks. Using these rail-partitioned blocks, a sparse solver can identify potential partitions, but eliminate fill-ins as determined by the topological analysis. A cost function can be applied to the potential partitions as well as the identified cuttable/un-cuttable devices to determine final cut points in the circuit and dynamic inputs to the final blocks. Simulation can be performed on the final blocks and simulation results can be generated.

Abstract: A rackmount chassis includes removable supports that provide interior support for blades having mounting edge-to-mounting edge dimensions that are less than the full chassis width. The removable supports are mounted on parallel support plates that span the full width of the chassis. Each removable support supports an edge of at least one blade installed into the rackmount chassis. The locations of the removable supports on the parallel support plates determine the blade form factors (mounting edge-to-mounting edge dimensions) that the rackmount chassis can accept. Because the removable supports can be individually removed/installed, the configuration of the resulting rackmount component can be changed without physically removing the rackmount component from the rack in which it is mounted.

Abstract: The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

Abstract: A self-adjusting solar light transmission (daylighting) apparatus includes a sunlight concentrating member (e.g., a lens array) for concentrating direct sunlight in focal zone regions disposed inside a sheet containing an evenly-distributed stimuli-responsive material (SRM) that has a relatively high transparency state in the absence of concentrated sunlight, and changes to a relatively opaque (light scattering or absorbing) state in small portions located in the focal zone regions in response to concentrated direct sunlight. Thereby, 80% or more of direct sunlight is prevented from passing through the apparatus, but 80% or more of diffuse light is passed. The outer sheet surfaces are locally parallel (e.g., planar) such that sunlight scattered by the light-scattering SRM portions is transmitted by total internal reflection through the remaining transparent sheet material, and outcoupled to one or more optional solar energy absorbing structures (e.g.

Abstract: An ambient country identifier (ACI) signal can be used to automatically provide location awareness for a WLAN device. If an ACI signal is detected, then the WLAN device can configure itself to comply with channel and power settings for the country having the detected ACI signal. After detection of the ACI signal, the WLAN device can be “locked” to the country having that ACI signal, thereby ensuring legal operation of the WLAN device even after subsequent restarts. If an ACI signal is not detected, then the WLAN device can be configured in a default mode, e.g. an “open mode” in which end users can configure the WLAN device by entering a country of operation or a “common mode” in which the channel and transmit power settings meet global spectrum usage requirements.

Abstract: A dual-mode switching voltage regulator has a duty cycle that varies with the input and output voltages so as to dynamically compensate for changes in the operating conditions. The switching voltage regulator uses input and output voltages/currents to optimize the duty cycle of the signals applied to a pair of switches disposed in the regulator. In the PFM mode, a control block senses the time that a first switch used to discharge an inductor is turned off. If the control block senses that the first switch is opened too early, the control block increases the on-time of a second switch used to charge the inductor. If the control block senses that the first switch is opened too late, the control block decreases the on-time of the second switch.

Abstract: A method for generating a linear piecewise representation of a driver output current signal includes segmenting the driver output current signal such that an integral of each segment matches an actual voltage change in corresponding portion of an associated output voltage signal (within a desired tolerance). The beginning and ending current/time values for each segment can then be compiled into the piecewise linear representation of the driver output current signal. A method for generating a model driver output current signal includes conformally mapping first and second sets of precharacterization output current data based on a weighted average of the indexing parameter (e.g., input slew or output capacitance) values for the model driver output signal and the first and second sets of precharacterization data.

Abstract: Using phase shifting on a mask can advantageously improve printed feature resolution on a wafer, thereby allowing greater feature density on an integrated circuit. Phase shifting can create an intensity imbalance between 0 degree and 180 degree phase shifters on the mask. An improved method of designing an alternating PSM to minimize this intensity imbalance is provided. Sub-resolution features, called “blockers”, can be incorporated in the alternating PSM design. Specifically, blockers can be formed in the 0 degree phase shifters. In this configuration, the intensity associated with the 0 degree phase shifters approximates the intensity associated with the corresponding 180 degree phase shifters. Intensity balancing using blockers retains image contrast, thereby ensuring printed feature quality.

Abstract: A method of forming spring structures using a single lithographic operation is described. In particular, a single lithographic operation both defines the spring area and also defines what areas of the spring will be uplifted. By eliminating a second lithographic operation to define a spring release area, processing costs for spring fabrication can be reduced.

Abstract: A line driver includes current sources and resistors that form a bridge circuit in which a bridge resistor is connected between an internal node and ground, and a series resistor connected between the internal node and the driver's output node. The internal node is connected to receive a unit current from a first stage transistor, and the output node is connected to receive an amplified current from a second stage transistor that is N times the unit current. The bridge resistor is formed with a resistance value set such that the voltages at the internal node and the output node are equal, i.e., such that no current flows through the series resistor. The resistance value of the series resistor is thus adjustable to optimize output impedance in a manner independent of the driver's gain. An echo cancellation circuit is utilized to eliminate noise from two associated line drivers.

Abstract: A receiver for receiving both GPS signals and GLONASS signals is provided. This receiver includes an analog front end (AFE), a GPS digital front end (DFE) and a GLONASS DFE for receiving an output of the AFE, and a dual mode interface (DMI) for receiving outputs of the GPS and GLONASS DFEs. Search engines are provided for receiving outputs of the DMI. Notably, certain front-end components of the AFE are configured to process both the GPS signals and the GLONASS signals.