Abstract: A method for determining portions of a GPS satellite signal may use non-coherent integration to determine a repeated pattern such as a preamble. Once the repeated pattern is determined, portions of the GPS satellite signal that may be determined with partial correlation sums. Sensitivity to satellite signals may be increased by computing more partial correlation sums on portions of the GPS satellite signal. In one embodiment, time of day information may be determined from the GPS satellite signal with partial correlation sums.

Abstract: Systems and methods for communicating using various protocols through the Secured Digital (SD) physical interface are disclosed. The invention covers, among others, single-mode and multi-mode hosts, single-mode and multi-mode devices, as well as techniques for initializing these hosts and devices in order to facilitate the aforementioned communication.

Abstract: Wafer-based solar cells are efficiently produced by extruding a dopant bearing material (dopant ink) onto one or more predetermined surface areas of a semiconductor wafer, and then thermally treating the wafer to cause diffusion of dopant from the dopant ink into the wafer to form corresponding doped regions. A multi-plenum extrusion head is used to simultaneously extrude interdigitated dopant ink structures having two different dopant types (e.g., n-type dopant ink and p-type dopant ink) in a self-registered arrangement on the wafer surface. The extrusion head is fabricated by laminating multiple sheets of micro-machined silicon that define one or more ink flow passages. A non-doping or lightly doped ink is co-extruded with heavy doped ink to serve as a spacer or barrier, and optionally forms a cap that entirely covers the heavy doped ink. A hybrid thermal treatment utilizes a gaseous dopant to simultaneously dope exposed portions of the wafer.

Abstract: Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.

Abstract: This invention pertains to the field of creating incentives for the completion of the design of integrated electronic circuits (chips). Modern chip design use sophisticated computer aided design software (CAD tools). Typically, CAD tools are sold or rented with pricing schemes that restrict the number of copies and usage of the software and are accompanied by a time-based maintenance charge. These pricing schemes do not encourage cooperation and business efficiency. In one embodiment of the invention, a CAD tool vendor receives two payments, one for access to the technology, providing unlimited usage and copies of the software, and a second payment when the technology produces a useful result. This connects vendor payment to the success of the customer. The vendor finds it advantageous to create tools that are easy to learn, easy to use, and with all the necessary functionality.

Abstract: An extrusion head is disposed over a substrate, and material is extruded through an oblique (e.g., semi-circular or tapered) outlet orifice of the extrusion head to form an associated extruded structure having an equilibrium shape that resists settling after being deposited on the substrate. The extrusion head includes fluidic channels having a flat surface formed by a flat first (e.g., metal) sheet, and an oblique (e.g., substantially semi-cylindrical) surface formed by elongated oblique trenches that are etched or otherwise formed in a second sheet. The fluidic channel communicates with the outlet orifice, which has a flat edge formed by the first sheet, and an oblique edge formed by an end of the oblique trench. The material is extruded through the outlet orifice such that its flat lower surface contacts the substrate, and its oblique upper surface faces away from the substrate. Two materials are co-extruded to form high aspect-ratio gridlines.

Abstract: A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. In another aspect, a system differentiates between data bits based on their estimated reliability, giving more emphasis to decoding reliable bits than unreliable bits using any of a variety of techniques. By differentiating between good and bad bits and de-emphasizing or ignoring unreliable bits, the system can provide a significant reduction in uncorrectable errors and packet loss.

Abstract: A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.

Abstract: A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage VPP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.

Abstract: A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate a new output current, when can be used to update the output voltage once again across the next time increment. By repeating this process across a time frame for the model output signal, a model output current and output voltage signals can be generated that match the actual output current and voltage signals from a driver in a multi-driver system.

Abstract: A method and apparatus for detecting radar signals in single and multiple (extension) channel wireless network frequencies uses spectral and DC analysis. Spectral images produced through a Fast Fourier transform may be captured and analyzed to determine if any radar signals may be present within the selected wireless network frequencies. A plurality of spectral images may also be analyzed to determine if frequency shifting radar signals are present as well. DC analysis of the power contained at the wireless carrier frequencies may detect radar signals that may be centered near those frequencies.

Abstract: A Cassegrain-type concentrating solar collector cell includes primary and secondary mirrors disposed on opposing convex and concave surfaces of a light-transparent (e.g., glass) optical element. Light enters an aperture surrounding the secondary mirror, and is reflected by the primary mirror toward the secondary mirror, which re-reflects the light onto a photovoltaic cell mounted on a central region surrounded by the convex surface. The primary and secondary mirrors are preferably formed as mirror films that are deposited or plated directly onto the optical element. A concentrating solar collector array includes a sheet-like optical panel including multiple optical elements arranged in rows. The photovoltaic cells are mounted directly onto the optical panel, and the primary mirrors of the individual collector cells include metal film segments that are coupled by the photovoltaic cells to facilitate transmission of the generated electrical energy.

Abstract: A system for characterizing material properties in miniature semiconductor structures performs a scatterometry analysis on inelastically scattered light. The system can include a narrowband probe beam generator and a detector. A single wavelength probe beam from the narrowband probe beam generator produces scattered light from a measurement pattern on a test sample. The scattered light is measured by the detector, and the measurement data (e.g., Raman spectrum) is used in a scatterometry analysis to determine material properties for the measurement pattern. The detector can measure either incoherent inelastically scattered light (e.g., using a spectrometer) or coherent inelastically scattered light (e.g., using an array detector). If the measurement pattern dimensions are substantially similar to actual device dimensions, the material property distributions determined for the measurement pattern can be applied to the actual devices on the test sample.

Abstract: Providing duty cycle correction can include determining whether a clock signal has a duty cycle greater than 50% based on averaging the clock signal and comparing that averaged clock signal to ½ VDD. When the duty cycle is greater than 50%, the clock signal can be selected. When the duty cycle is less than 50%, the inverted clock signal can be selected. Thus, a duty cycle corrected clock signal can be generated based on the clock signal or the inverted clock signal. Notably, a duty cycle control signal can be adjusted based on comparisons of an averaged, duty cycle corrected clock signal and predetermined low/high voltage ranges. Components performing comparing functions can be strobed based on a count performed on the clock signal.

Abstract: A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the output clock signal. The switched terminated load uses transistors having the same size as transistors in the output buffer. The switched terminated load draws the same DC current as the output buffer. As a result, the switched terminated load and the output buffer have the same electro-migration performance. Pull-up and pull-down MOS impedances of the switched terminated load are easily adjusted during switching periods of the switched terminated load. The design of the switched terminated load minimizes variations in the terminated load impedance due to MOS impedance variations.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: Accurate position capability can be quickly provided using a Wireless Local Area Network (WLAN). When associated with a WLAN, a wireless device can quickly determine its relative and/or coordinate position based on information provided by an access point in the WLAN. Before a wireless device disassociates with the access point, the WLAN can periodically provide time, location, and decoded GPS data to the wireless device. In this manner, the wireless device can significantly reduce the time to acquire the necessary GPS satellite data (i.e. on the order of seconds instead of minutes) to determine its coordinate position.

Abstract: A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create an unwound design, and then applying logic reduction techniques to the unwound design using the clock-like signals to reduce (simplify) the logic in the unwound design by eliminating unused/unnecessary registers, inputs, outputs, and logic. The resulting phase-abstracted design can then be processed much more efficiently by functional verification engines than the original multiphase circuit design due to the reduced number of registers/inputs.

Abstract: A non-atmospheric pressure vapor oven system that utilizes a controllable pressure zone to facilitate fast phase change heat transfer at any desired temperature to heat or cool flat substrates, and to level temperatures across different locations of the substrates. The system enables the use of a heat transfer fluid, such as water, without being limited to a particular temperature, such as the fluid's natural boiling point at atmospheric pressure. The system includes a vapor oven (hermetic enclosure) defining a pressure chamber having sealed entry and exit ports for transferring an object (e.g., a sheet of paper) with added material (e.g., toner) through the pressure chamber, and a pressure regulation apparatus for setting the saturation temperature (boiling point) of heat transfer fluid inside the vapor oven to an optimal heating/cooling temperature by selectively controlling the pressure inside the hermetic enclosure.

Abstract: Black matrix (BM) material is deposited on glass and patterned to form walls that define an array of wells. Various surface treatments and masking schemes are utilized to achieve surface energy control of the BM glass. The surface treatments include one or more of chemically treating the BM walls by depositing hydrophobic self-assembled monolayers on the uppermost wall surfaces, and plasma treatments to control the surface energy of the various BM glass surfaces. Masking processes include backside exposure and development of photoresist, and maskless, self-aligned photo-patterning of the monolayers. Color filter ink is then injected into each well from an ink jet print head. The high surface energy of the lower and side wall surfaces facilitates wetting of the ink, and the low surface energy of the monolayers prevents intermixing of ink between adjacent wells. The ink then dries to form a color filter in each well.