Abstract: A radiotherapy appliance having a plurality of controllable radiation beams which converge on a focus volume wherein an object being irradiated can be movably positioned relative to the focus volume for varying time periods and with varying radiation exposure rates, optimally under control of a computer. The computer controls the focus volume radiation beam size, intensity, and exposure time for subareas of the treatment target in response to a radiation dose distribution determined for the treatment target. A determination of the radiation beam size, intensity, and dwell time of the focus volume in the target area, is made by initially dividing up the specified treatment area into volume elements or voxels and having biological characteristics of the treatment area assigned to each voxel. The energy deposition incident to each voxel to provide this biological characteristic is then calculated.

Abstract: The present invention is a method for bonding a lubricant onto the surface of rotating storage media. In particular, the method bonds reactive and non-reactive lubricants onto the carbon based protective coating of a magnetic storage disk. The lubricant is first applied onto the disk surface through conventional coating techniques, such as dipping, spinning, spraying, or vapor deposition. The thickness of the applied coating is thicker than the final bonded thickness of the lubricant. Typically, the applied thickness of the film is approximately 30 Angstroms. The lubricant coated disk surface is then exposed to low energy electron irradiation. The energy level of the accelerated electrons is below 100 eV. The lubricated film is exposed to a dosage level of approximately 1000 microcoulombs per square centimeter. This dosage level bonds approximately 15 Angstroms of lubricant to the disk surface. The non-bonded or excess lubricant is then rinsed off in a liquid freon or other suitable rinse.

Abstract: A radiotherapy appliance having a plurality of controllable radiation beams which converge on a focus volume wherein an object being irradiated can be movably positioned relative to the focus volume for varying time periods and with varying radiation exposure rates, optimally under control of a computer. The computer controls the focus volume radiation beam size, intensity, and exposure time for subareas of the treatment target in response to a radiation dose distribution determined for the treatment target. A determination of the radiation beam size, intensity, and dwell time of the focus volume in the target area, is made by initially dividing up the specified treatment area into volume elements or voxels and having biological characteristics of the treatment area assigned to each voxel. The energy deposition incident to each voxel to provide this biological characteristic is then calculated.

Abstract: A radiotherapy appliance having a plurality of controllable radiation beams which converge on a focus volume wherein an object being irradiated can be movably positioned relative to the focus volume for varying time periods and with varying radiation exposure rates, optimally under control of a computer. The computer controls the focus volume radiation beam size, intensity, and exposure time for subareas of the treatment target in response to a radiation dose distribution determined for the treatment target. A determination of the radiation beam size, intensity, and dwell time of the focus volume in the target area, is made by initially dividing up the specified treatment area into volume elements or voxels and having biological characteristics of the treatment area assigned to each voxel. The energy deposition incident to each voxel to provide this biological characteristic is then calculated.

Abstract: The objects of this invention are accomplished by rearranging the DCT process such that non-trivial multiplications are combined in a single process step. In particular, the DCT equations for the application of the two-dimensional DCT process on k.times.k points are factored into 1) a permutation matrix, 2) a diagonal matrix, and 3) a matrix whose product with an arbitrary vector having k.sup.2 points requires considerably fewer non-trivial multiplications. Furthermore, in some cases none of these non-trivial multiplications are nested; that is, no output of a non-trivial multiplication is ever involved in another multiplication operation. The diagonal matrix is not unique for any set of data. Once the diagonal matrix elements are chosen the remaining factors are developed. When the factorization is complete, the diagonal matrix is absorbed into the quantization step which follows the DCT process. The quantization step is the multiplication of a diagonal matrix by the DCT output data.

Abstract: A floating gate is inserted into the gate stack of an EEPROM cell. For an N channel EEPROM device, the floating gate is composed of a material having a conduction band edge (or fermi energy in the case of a metal or composite that includes a metal) at least one and preferably several kT electron volts below the conduction band edge of the channel region. The floating gate material thus has a larger electron affinity than the material of the channel region. This allows the insulator separating the floating gate and the channel to be made suitable thin (less than 100 angstroms) to reduce the writing voltage and to increase the number of write cycles that can be done without failure, without having charge stored on the floating gate tunnel back out to the channel region during read operations.

Abstract: This invention relates generally to the accessing of random access access memory arrays and, more specifically to circuits and techniques for increasing the data valid time of such memory arrays without increasing either the access or cycle times of the array. This is accomplished by providing, during a read cycle, a read signal directly to an output driver and simultaneously providing, via a parallel path, a latch output to the same driver. The latch output is provided under control of the read signal and a returning portion of a clock pulse such that the latch output overlaps the direct read signal from a read/write amplifier. An output is provided from the latch until it is reset and may last well into the next read cycle even when a new read signal is present.

Abstract: The present invention is a fully integrated digital filter which interacts with a phase comparator to provide a phase lock loop and data retiming function. The digital filter includes a prescaler, a six bit reversible counter, and a four bit reversible counter. The phase comparator is a D-type edge-triggered flip-flop in which an input data signal clocks the flip-flop and samples a clock signal to determine whether the clock signal leads or lags the input data signal. The clock signal is repeatedly sampled and the digital filter counts the number of leading and lagging signals. The digital filter counts the leading and lagging signals in groups so that the counting rate of the digital filter does not have to be as high as the input data rate. The prescaler groups the bits and the six bit counter determines the number of samples that indicate a clock lead or lag.

Abstract: The present invention is a hetero superlattice pn junction. In particular, the invention combines n and p type superlattices into a single pn junction having a bandgap sufficient to create high frequency (i.e. blue or higher) light emission. Individual superlattices are formed using a molecular beam epitaxy process. This process creates thin layers of well material separated by thin layers of barrier material. The well material is doped to create carrier concentrations and the barrier materials are chosen in combination with the thickness of the well materials to adjust the effective bandgap of the superlattice in order to create an effective wide bandgap material. The barrier material for the n and p type superlattices is different from the material used to form either of the two types of well layers.

Abstract: The present invention is a structure and method for controlling the depth of an etching process. In particular, the method and structure of the present invention creates a marker layer which resides between a layer to be etched and a protected layer. The marker layer is detected during the etch process and the etch process is controlled based on the detection of the marker layer. The marker layer has physical characteristics which are very similar to the layers being etched or protected. The marker layer has a similar lattice constant and electrical behavior to either the etched layer or the protected layer. The marker layer has very different optical properties from the etched or protected layers so that even a thin marker layer can be easily detected using in-situ ellipsometric measurements. A specific embodiment of the present invention is a layer of SiGe interposed between a thick silicon layer and a thin silicon layer.

Abstract: The present invention is a translator circuit which receives an input compatible with a differential current switch type of circuit and transmits an output compatible with a super buffer logic type of circuit. The translator circuit has a gain stage interposed between an input and output stage which both level shift the signal downward. The gain stage provides the translator circuit with the performance necessary to avoid attenuation of the signal between receiving the input signal and transmitting the output signal. The input and output stages buffer the gain stage by shifting the voltage level of the translator downward in two stages. The translator circuit provides its own voltage reference circuits which are compatible with the power supply of the DCS and SBL circuits. The reference circuits are self compensating for temperature effects. The translator circuit of the present invention allows different types of circuit families to be inexpensively designed on the same integrated circuit chip.

Abstract: The interface circuit of the present invention adjusts the signal voltage across a leaking transistor such that the leakage is reduced while also shunting out the adjustment means when the adjustment means impedes the operation of the interface circuit. One embodiment of the present invention is a level translator comprised of a level shifting stage coupled to a buffer stage. The level shifting stage has its power source coupled to a current shunting device. The current shunting device is connected in parallel across the first P-channel device of the level shifting stage. The first P-channel device of the level shifting stage is connected in series with a second P-channel device having its drain connected to a drain of a first N-channel device wherein the first N-channel device has its source connected to a drain of a second N-channel device. The current shunting device is formed from a single P-channel device.

Abstract: This invention is a three layer Si.sub.x Ge.sub.1-x structure formed on a silicon substrate in which a thin, lightly doped Si.sub.x Ge.sub.1-x layer is formed between two heavily doped Si.sub.x Ge.sub.1-x layers. The incorporation of at least 10% germanium in the silicon provides for intervalley scattering of carriers in the conduction band of the Si.sub.x Ge.sub.1-x layers. This intervalley scattering leads to the negative differential conductance necessary for transferred electron device (TED) operation. Additionally, the lightly doped Si.sub.x Ge.sub.1-x layer is made very thin, on the order of 2,000 to 7,000 Angstroms, and the current flow through the this layer is vertical so that a high electric field can be placed across the lightly doped layer without applying a high voltage across the lightly doped layer. The lightly doped layer can be made thin even though it is interposed between two heavily doped layers because the growth of the in-situ doped Si.sub.x Ge.sub.

Abstract: This invention describes a low resistance contact structure to n-type GaAs and a method for making such a contact structure. The contact structure is formed by depositing successive layers of Ni, Au, Ge, and Ni. A fifth layer is then deposited on the first four layers. The fifth layer is a metallic tungsten oxide. The metallic tungsten oxide is formed by sputtering tungsten onto the 4 layer stack in a low pressure argon plus oxygen atmosphere. The resulting 5 layer stack is then annealed in a rapid thermal anneal (RTA) process. The RTA process heats the stack for 5 seconds at 600 degrees. The resulting structure consists of an intermetallic NiGe compound having a small amount of a AuGa compound dispersed within it and being covered by a metallic tungsten oxide film. The oxygen from the metallic tungsten oxide film acts as a gettering mechanism to create gallium vacancies in the GaAs lattice structure during the RTA process.

Abstract: The objects of the present invention are accomplished by merging a MOSFET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region of the transfer FET of the EEPROM cell. The heavily doped source and drain regions are formed on two vertical sidewalls of the trench and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench are formed by isolation oxide. A first silicon dioxide layer covers the bottom of the trench and forms part of the gate oxide of the cell device. A second silicon dioxide layer covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer.

Abstract: The present invention is an isolation structure for use with FET or bipolar devices incorporating a silicon-germanium layer in which the semiconductor devices are isolated by trench structures. A trench is etched through a pad layer, a single crystal silicon layer, a silicon-germanium layer, and finally, into the silicon substrate. The silicon-germanium layer is interposed between the single crystal silicon layer and the silicon substrate and the pad layer covers the single crystal silicon layer. The trench sidewall exposes the silicon-germanium layer. A single crystal silicon layer is formed as a trench liner. This silicon trench liner is then oxidized to passivate the trench isolation. The trench can then be filled with a dielectric without the devices being affected by parasitic leakage caused by the silicon-germanium layer exposed by the trench isolation.

Abstract: The objects of the present invention are achieved by forming a high voltage generating circuit which comprises: a flyback transformer having a primary winding and a secondary winding; means for supplying pulses of first frequency to the primary winding; a smoothing capacitor connected across the secondary winding; an output line connected to one terminal of the smoothing capacitor; means for detecting a variation of high voltage on the output line to generate compensating voltage pulses of a second frequency which is higher than the first frequency for compensating the variation of high voltage to supply the compensating voltage pulses to the other terminal of the smoothing capacitor. Additionally, a low pass filter is connected between the other terminal of the smoothing capacitor and the secondary winding, which prevents the compensating voltage pulses from being supplied to the secondary winding.

Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon on a plurality of substrates in a hot wall, isothermal deposition system is described. The deposition temperatures are less than about 800.degree. C., and the operating pressures during deposition are such that non-equilibrium growth kinetics determine the deposition of the silicon films. An isothermal bath gas of silicon is produced allowing uniform deposition of epitaxial silicon films simultaneously on multiple substrates. This is a flow system in which means are provided for establishing an ultrahigh vacuum in the range of about 10.sup.-9 Torr prior to epitaxial deposition. The epitaxial silicon layers can be doped in-situ to provide very abruptly defined regions of either n- or p-type conductivity.

Abstract: The present invention is the use of coupled quantum wells in the active region of a semiconductor laser to modulate the frequency and amplitude of the light output of the laser. In a particular embodiment of the present invention the coupled quantum wells are contained in a graded index of refraction semiconductor double heterostructure laser. The active region of this tunable laser consists of two quantum wells having a width of approximately 50 Angstroms or less which are separated by a barrier layer having a width of approximately 20 Angstroms or less. The quantum well material is intrinsic GaAs and the barrier layer is Al.sub.x Ga.sub.1-x As wherein x=0.23. The active region is surrounded by the double heterostructure in which one side is doped p-type and the second side is doped n-type. The resulting laser is a p-i-n type structure.

Abstract: Disclosed is a new method suitable for making highly integrated quantum wire arrays, quantum dot arrays in a single crystal compound semiconductor and FETs of less than 0.1 micron gate length. This makes it possible to construct a high-performance electronic device with high speed and low power consumption, using a combination of low-temperature-growth molecular beam epitaxy (LTG-MBE) and focused ion beam (FIB) implantation. The compound semiconductor (GaAs) epitaxial layers, which are made by LTG-MBE, are used as targets of Ga FIB implantation to make Ga wire or dot arrays. Precipitation of arsenic microcrystals, which are initially embedded in a single crystal GaAs layer and act as Schottky barriers, are typically observed in an LTG GaAs layer. A thermal annealing process, after implantation, changes the arsenic microcrystals to GaAs crystals if the arsenic microcrystals are in the region in which the Ga ions are implanted.