Abstract: The present invention is an isolation structure for use with FET or bipolar devices incorporating a silicon-germanium layer in which the semiconductor devices are isolated by trench structures. A trench is etched through a pad layer, a single crystal silicon layer, a silicon-germanium layer, and finally, into the silicon substrate. The silicon-germanium layer is interposed between the single crystal silicon layer and the silicon substrate and the pad layer covers the single crystal silicon layer. The trench sidewall exposes the silicon-germanium layer. A single crystal silicon layer is formed as a trench liner. This silicon trench liner is then oxidized to passivate the trench isolation. The trench can then be filled with a dielectric without the devices being affected by parasitic leakage caused by the silicon-germanium layer exposed by the trench isolation.

Abstract: These superconducting circuit elements, namely SNS heterostructures, such as, e.g. Josephson junctions and field-effect transistors, have a sandwich structure consisting of at least one layer of high-T.sub.c superconductor material arranged adjacent to a metallic substrate, possibly with an insulating layer in between, the substrate, the superconductor and--if present--the insulator all consisting of materials having at least approximately matching molecular structures and lattice constants. Electrical contacts, such as source, drain and gate electrodes are attached to the superconductor layer and to the substrate, respectively. The electrically conductive substrate consists of a metallic oxide such as strontium ruthenate Sr.sub.2 RuO.sub.4, whereas the superconductor layer is of the copper oxide type and may be YBa.sub.2 Cu.sub.3 O.sub.7-.delta., for example. The insulator layer (10) may consist of SrTiO.sub.3.

Abstract: A method of proximity correction in an E-beam lithography system wherein each design shape is contracted by a predetermined bias and the E-beam dose required at any given point of the design is determined such that each of the design shapes is enlarged, on development, by the value of the predetermined bias, the determination of the E-beam dose being made in accordance with a predetermined relationship between an indicator, such as the electron backscatter, and the required E-beam dose, the indicator being defined for a plurality of points arranged on a coarse grid on the design and being indicative of the degree of the proximity effect at the respective point, the determination of the required dose being made by solving, at each of the plurality of points on the design, an integral equation relating the indicator to the E-beam dose distribution.

Abstract: The present invention demonstrates a rotating media storage system which quickly measures and accurately compensates for thermal and mechanical errors in the position of the data detector with respect to the written data. This is accomplished by measuring the error rate of the written data as a function of the read offset of the detector. Error rates become increasingly large as the sensed noise to signal ratio becomes large. The present invention counts the number of errors detected in reading written data for various read offsets when the data storage system is initially activated. When the number of errors reaches a target rate, the read offset required to produce the target rate is saved. This procedure is performed on either side of the data track. The detector is then centered between the two offsets. During the operation of the storage system, thermal and mechanical errors are introduced into the detector position compensation means.

Abstract: The invention is a method of designing an integrated circuit in which the steps of designing the circuit are optimized by a formal hierarchy. This method, called Timing Driven Placement, of designing an integrated circuit avoids detailed optimization which consumes enormous computational resources. It organizes physical and logical characteristics of the design so that those characteristics can be optimized with respect to the physical design of the circuit. The characteristics are optimized and the resulting circuit to location assignment is placed and wired with a conventional automated process. The method optimizes the global placement into precincts of logic segments of the circuit design with respect to the segment placement effect on circuit timing and wireability. The method then migrates individual circuits within particular segments to other segments to improve both the individual segment and overall circuit timing and wireability.

Abstract: The present invention relates to an interconnected array of photodetector cells in which each cell of the photodetector array contains a photodetector for detecting light pulses and a photodetector for switching on the photodetector cell. Each cell has a first and second busbar between which the photodetectors pass current in response to light impinging on the cell. The cells of the array are connected in parallel by the first and second busbars. The photodetectors are formed by depositing electrodes connected to the first and second busbars onto GaAs. The photodetector for detecting light pulses has a significantly faster response to impinging light than the photodetector for switching on the photodetector cell. The faster response of one photodetector with respect to another photodetector can be accomplished by reducing the spacing on GaAs between electrodes forming the faster photodetector, or by adding an integrating capacitor to one photodetector.

Abstract: This invention implements a cache access system that shortens the address generation machine cycle of a digital computer, while simultaneously avoiding the synonym problem of logical addressing. The invention is based on the concept of predicting what the real address used in the cache memory will be, independent of the generation of the logical address. The prediction involves recalling the last real address used to access the cache memory for a particular instruction, and then using that real address to access the cache memory. Incorrect guesses are corrected and kept to a minimum through monitoring the history of instructions and real addresses called for in the computer. This allows the cache memory to retrieve the information faster than waiting for the virtual address to be generated and then translating the virtual address into a real address.

Abstract: This invention reduces the Delta I noise on an integrated circuit chip by reducing the changes in current supply required for transitions in logic states of the input/output devices. The invention uses a 3/6 binary code for communicating between integrated circuit chips. This code uses six bits to represent the 16 hex code digits typically used for computer instructions. Three of the six bits are in a high logic state and three of the six bits are in a low logic state for all 16 hex code representations. Therefore, changing from any one logic state to another, does not change the overall current supply required by the six input/output devices. Groups of six input/output devices (corresponding to the 3/6 code) are located relatively close to each other with respect to the power supply pins which supply current to the six input/output devices. As a result, there is a high to low transition for every low to high transition over similar parasitic impedances on the input/output devices.

Abstract: A keyless tool chuck sleeve is provided for rotary tools which features an elastomeric cover integrally molded to the chuck sleeve to improve the operator's grip during opening and closing of the chuck. The chuck sleeve of the present invention further provides for an abrasion resistant nose, and bit centering and dust guard capabilities.

Abstract: The present invention accomplishes the above objects by employing a display having the capability to emit light and form images viewable from both the front and back of the display. The invention also shutters the images displayed on the front and back of the display so that the images can be correctly displayed depending on the viewpoint of the viewer. Text and images displayed such that they are seen from both the front and back of the display appear differently to the front and rear viewer. Electronic shutters are placed between the display and both the front and rear viewers so that they can be flashed on and off fast enough to provide a stable image appearing to each viewer. The shutters also flash slow enough so that display data can be rewritten to provide each viewer with a correct image. The correct image can be either the corrected image of that image seen by the opposing viewer, or a completely separate image. In this way, simultaneous images appear to both the front and rear viewer.

Abstract: A sequence of instructions made up of stages is executed sequentially by the processor in a first mode (stack mode) such that, the Nth stage of the Ith instruction is processed simultaneously with the N+1 stage of the I-1 instruction. Similarly the N+1 stage of the I-1 instruction is processed at the sasme time as the N+2 stage of the I-2 instruction and so on. The processing unit maintains the execution of instructions in the same sequence as they were received by the processing unit by executing all sections of an instruction. Even though a stage may not be required for execution of a particular instruction, the processor must wait (i.e., execute a null instruction) for a time equivalent to a stage before processisng the next stage. The invention provides a second mode (non-stack mode) of execution such that unneeded or null instruction stages are bypassed without the processing order of the execution sequence being disturbed.

Abstract: The invention is an improvement in a liquid crystal display device of the type having spaced front and rear glass panels, a transparent electrode layer, and an array of individually addressable pel electrodes separated from the transparent electrode layer by a cavity filled with liquid crystal material. The improvement comprises a color filter layer in the form of a decal pattern. The decal pattern is formed using interference film techniques which form an inorganic color filter. The decal is placed on one of the glass panels using known decal transfer methods. The inorganic nature of the color filter layer and the decal transfer methods allow for enhanced optical density of the color liquid crystal display.

Abstract: Workstations are connected via workstation controllers to two computer systems where one of the workstation controllers is a primary or controlling workstation controller and the other workstation controller is connected to appear to the primary workstation controller as a workstation and is designated as the secondary or standby workstation controller. The standby workstation controller has its line impedance matching resistor connected to function as a line terminator but it can also function as a line driver resistor when the primary or controlling workstation controller fails, the failure of the primary or controlling workstation controller being detected by the secondary or standby workstation controller upon the failure of being polled by the primary or controlling workstation controller within a predetermined period of time. The line impedance matching resistor of the failing primary or controlling workstation controller then functions as a line terminator resistor.

Abstract: The present invention implements self testable boundary logic by using a tristate pass gate and a tristate receiver in combination with a linear feedback shift register, a storage register, and level sensitive scan design (LSSD) techniques. The linear feedback shift register (LFSR) shifts data into a storage register which is connected to the data inputs of the boundary logic through the tristate pass gate. The outputs of the tristate input receiver are also connected to the inputs of the boundary logic so that the boundary logic can receive data from both the data input of the integrated circuit (data path) or from the storage register connected to the LFSR. The tristate pass gate and receiver are enabled through a self test signal such that when the pass gate is enabled the receiver is not enabled and vice versa. In this way the boundary logic can only get data from either the storage register or through the receiver but not both.

Abstract: This invention provides an interposer for electrically connecting two substrates with high density interconnections. The interposer comprises an elastomeric material surrounding fine metal wires which extend through the elastomeric material. The elastomeric material provides mechanical support and electrical isolation for the wires which connect the two opposing surfaces of the interposer with mating substrates. One surface of the interposed has scribes cut into it which mechanically isolate the individual wires. This mechanical isolation between wires reduces the stress placed on the substrates from being connected when the interposer is compressed between the substrates. The support given individual wires by the elastomeric material is controlled, by adjusting the spacing and widths of the scribes, to provide uniform compression across the substrates.

Abstract: The present invention utilizes bypass circuitry to shorten the cycle time of a cache memory by shortening the time required to perform a write through read operation (WTR). The bypass circuitry senses when a WTR operation will occur by comparing the encoded read and write addresses to determine when the encoded addresses are equal. When the encoded addresses are equal, a WTR operation is requested and the bypass circuitry sends the data to be written into memory to both the write address location and the cache output buffer. The bypass circuitry does not wait to access the data from the memory cells through the read decode, rather, it directly sends the data to the output buffer. The bypass circuitry provides a parallel read and write operations instead of serial operations during a WTR, thereby shortening the machine cycle time.

Abstract: This invention provides a means for suppressing radiated electromagnetic radiation in high current AC/DC power supplies. This radiation is the result of rectifier diode transient noise which is propagated through the electrical network of the power supply. The transient noise is propagated through the electrical and mechanical connections of the diodes to the transformer secondary. These connections have stray impedance which allows high frequency noise to be propagated through them. The stray impedances can be modulated to suppress the high frequency noise propagation without adding discrete inductor or capacitor elements to the electrical network. The modulation of the stray impedances is accomplished by adjusting the current sharing between rectifier diodes. This is accomplished by splitting the parallel connection between rectifier diodes, and making the connection of the diodes to the transformer secondary at various points along the secondary.

Abstract: A gate structure for integrated circuit devices which includes a work function layer, a low resistivity layer, and an electrically conductive barrier layer between the two other layers to prevent the other two layers from intermixing. The work function controlling layer is preferably selected from the group of tungsten, molybdenum, their silicides, or a combination thereof.

Abstract: The synthesis of hydride compounds by reacting both the ingredients of the compound and the hydrogen together in the presence of energy sufficient to ionize the hydrogen. An inert bombardment ingredient enhances efficiency. In situ generation of ingredients such as arsine is provided within the reactor adjacent the deposition site in chemical vapor deposition.

Abstract: A solder paste for use in a reducing atmosphere is disclosed. The solder paste includes a solder powder and an alcohol binder. The reducing atmosphere serves as a flux, thereby eliminating flux residues and the problems associated therewith. Solder splattering is reduced by using a polyhydric alcoholic binder which vaporizes or decomposes before the solder liquifies during heating. The use of such a solder paste in a reducing atmosphere results in no hazardous chemical by-products and, because the solder is handled in the form of a paste, is compatible with electrical components requiring precise dimensional tolerances.