Abstract: A pseudo ternary content addressable memory (PTCAM) device (100) can include a number of PTCAM blocks (102-0 to 102-63), each of which can include a number of standard PTCAM rows (106-0 to 106-63) and a standard memory row (104-0 to 104-63) for storing and providing mask information for the PTCAM rows. Redundancy for replacing a defective standard PTCAM row can be provided by a redundant section (108) that include fewer PTCAM rows than in a PTCAM block (102-0 to 102-63). Non-defective PTCAM rows within a standard PTCAM block containing a defective PTCAM row can continue to operate.

Abstract: A content addressable memory (CAM) (200) is disclosed that includes a value match mode, where a comparand value can be compared to a masked data value, and a range match mode where a comparand value can be compared to an upper range limit UR and a lower range limit LR. The CAM (200) may include a number of CAM cells (204-n to 204-0) that may each be connected to a compare section (109). A compare section (109) can include a first compare circuit (210) that may generate a match indication on a match line (212) and a second compare circuits (214-n to 214-0). A more significant second compare circuits (214-n) may provide upper and lower limit match results (UMn, LMn) to a less significant first compare circuit (210).

Abstract: A single ended input circuit can receive an input signal and generate a correction voltage corresponding to a common mode voltage of the input signal. A comparison of the input signal can be adjusted in response to the correction voltage. In one arrangement, an input circuit (100) can include a compare section (102) with first input (104-0) and second input (104-1). The first input (104-0) can receive an input signal (IN). The second input (104-1) can receive a reference voltage generated by a common mode detect and hold (CMDH) section (106). A (CMDH) section (106) can include an integrator circuit (108), an analog-to-digital (A/D) converter circuit (110), a digital hold circuit (112), and a digital-to-analog (D/A) converter (114). A correction voltage generated by integrating the input signal can be applied as the generated reference voltage.

Abstract: A memory device can include a group of memory cells, which can be arranged in a column (100) that receives power by way of a first cell supply nodes (106-0 to 106-m). A current limiter (110) can be situated between first cell supply nodes (106-0 to 106-m) and a power supply (VH), and limit a current (llimit) to less than a latch-up holding current (lhold_lu) for the group of memory cells (100). In a particle event, such as an ?-particle strike, a current limiter (110) can prevent a latch-up holding current (lhold_lu) from developing, thus preventing latch-up from occurring. Current limiter (110) can include p-channel transistors and/or resistors, and thus consume a relatively small area of the memory device.

Abstract: According to one embodiment, a content addressable memory (CAM) device (100) may include a number of CAM entry sets (102-0 and 102-1), each of which includes multiple CAM entries. CAM (100) may also include multiple programmable information registers (PIRs) (104-0 and 104-1), each of which can be associated with a CAM entry set (102-0 and 102-1). PIRs (104-0 and 104-1) may be accessed in response to CAM commands. Values stores in PIRs (104-0 and 104-1) may control access to associated CAM entry sets (102-0 and 102-1) and/or be output in response to predetermined operations in an associated CAM entry set (102-0 and 102-1).

Abstract: A circuit (100) can include a first section (102) that can provide a designated function within an integrated circuit device that can be altered due to current injection at a node (106). A mirror section (104) can mirror the effects of current injection on one or more devices within first section (102) and generate an output indication INJ_EFF representing such effects. In one very particular arrangement, detection of an injected current can be used to prevent false triggering of a switched electrostatic discharge (ESD) current path.

Abstract: A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each memory element (102-0 and 102-1). The memory elements (102-0 and 102-1) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (102-0 and 102-1) to the pre-write potential prior to providing write data via the bit lines (106-0 and 106-1).

Abstract: An oscillator circuit (100) can provide a dual slop temperature response. For a lower temperature range, a capacitor (106) can be charged and/or discharged according to a first current source (302) that provides an essentially constant current source. For a higher temperature range, the capacitor (106) can be charged and/or discharged according to a second current source (304) that can be enabled and/or provide current according to a voltage proportional to absolute temperature. A slightly positive temperature coefficient of a first current source (302) can be offset by a threshold detect circuit (210 and 212) within a second comparator circuit (204) that utilizes the threshold voltage (Vt) of a transistor (212) as a low limit for a capacitor voltage.

Abstract: A content addressable memory (CAM) device (200) can include a control block (202) having a dummy control circuit (216). A dummy control circuit (216) can initiate dummy searches (or other operations) prior to and/or during actual searches to reduce overall supply current transients. Methods for initiating dummy searches are also disclosed.

Abstract: Systems and methods for performing encoding and/or decoding can include an input data path that receives multiple input data values having an order (significance) with respect to one another. Each input data value can be applied to multiple compute paths (106-1 to 106-N), each of which can precompute multiple output values based on a different predetermined disparity value. Multiplexers (114-1 to 114-N) can output one precomputed output value according to a disparity value corresponding to a previous input data value in the order.

Abstract: A data path (200) can be configured to accommodate different clocking arrangements. In one mode, data values may be output at a single data rate: one data value every clock cycle. In another mode, data values may be output at a double data rate: two data values every clock cycle. A data path (200) can be compact circuit structure, needing only an additional mode multiplexer (206) and inverter over a conventional D-type master-slave flip-flop.

Abstract: A content addressable memory (CAM) device (200) can equalize a potential between a match line (202) and corresponding pseudo-supply (PVSS) line (204) in a pre-sense operation. In a sense operation, a sensing device (P4) can determine a match condition exists when the match line (202) potential varies from the PVSS line (204) potential. Complementary compare data lines (CD and BCD) can be equalized with one another in a pre-sense operation, while one compare data line (CD or BCD) can be equalized with bit lines (BB1 and/or BB2) in the sensing operation.

Abstract: A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic portion (108-0, 108-1) that receives the data stored therein. Memory areas and the logic portions of each memory/logic cell can be arranged on the substrate in a shape of an L, U, S, T, or Z to form a pair of interlocking memory/logic cells.

Abstract: A mask identification (ID) bit circuit (100) is disclosed that provides one of two potentials (VGND or VPWR) to a sense node (108). A mask ID bit circuit (100) may include a number of links (102-0 to 102-4) arranged in series. A link (102-0 to 102-4) may include inputs (104-0 and 104-1) and outputs (106-0 and 106-1). In one configuration, inputs (104-0 and 104-1) may be directly coupled to outputs (106-0 and 106-1). In another configuration, inputs (104-0 and 104-1) may be cross coupled to outputs (106-0 and 106-1). Cross coupling inputs (104-0 and 104-1) and outputs (106-0 and 106-1) of a link (102-0 to 102-4) can switch a potential (VGND or VPWR) supplied to a sense node (108). The configuration of more than one link (102-0 to 102-4) of a mask ID bit circuit (100) can be changed, allowing a sense node to be switched between two potential (VGND and VPWR) multiple times. According to an embodiment, n mask ID bit circuits (100) may provide as many as 2n different mask ID codes.

Abstract: A search engine system (100) and CAM device (300) are disclosed. A search engine system (100) may generate response packets (112) in response to requests packets (110) and include at least one content addressable memory (CAM) device (102-0) having an input interface (116-0) for receiving data packets and an output interface (116-1) for transmitting data packets.

Abstract: According to an embodiment, a content addressable memory (CAM) device (104) may be capable of executing a “restricted” search operation. A restricted search operation (an “explore” or “search beyond” operation) may compare only a portion of the CAM entries to a search key device. Preferably, a restricted search operation may restrict searches to entries having an index value greater than a received search index value.

Abstract: A multi-port memory cell (200) can be formed from seven transistors. Single ended write operations can be performed without a boosted word line voltage or variable power supply. A data value (D/DB) stored in the memory cell (200) can be cleared by shorting complementary data nodes (204-0 and 204-1) together. Write data can then be placed on a bit line. Complementary data nodes (204-0 and 204-1) can then be isolated once again, resulting in the write data being latched within the memory cell (300). An access method (700) for a multi-port memory cell is also described.

Abstract: A content addressable memory includes a priority encoder that is in communication with an array of the content addressable memory cells to receive match signals, and from the match signals generating an output index signal in accordance with a priority sequence of the match signals. The priority encoder has a plurality of input circuits to receive the match signals from the CAM array. A priority setting circuit receives a priority transformation signal indicating a priority index for modification of the priority sequence. An encoding circuit is in communication with the plurality of input circuits and the priority setting circuit for generating the output index signal in accordance with the priority sequence. The priority encoder circuit further includes an enabling circuit for receiving an enabling signal.

Abstract: A content addressable memory (CAM) device (400) can sequentially apply command and key data to different sections (404-1 to 404-4). Within each section, CAM cores (402-11 to 402-44) can be sequentially activated. Current surges when transitioning from an idle state to an active state, or vice versa, can be significantly reduced with additional latency but no loss in throughput.

Abstract: A defect current contribution elimination technique may be suitable for dynamic random access memories (DRAMs) and other memory devices. A defect current can be eliminated by using an isolation circuit (106) between bitlines (102-0 and 102-1) and an associated sense amplifier circuit (104). Isolation circuit (106) can be controlled by programmable elements, such as fusible links, which are blown at wafer test to isolate the defective bitlines from the sense amplifier circuit. Isolated, defective bitlines may initially float, but based upon the type of defect, such bitlines can be resistively tied to another element, and as a result no DC current will flow. According to another implementation, controllable devices are placed between wordlines (206) and the wordline driver circuits (226-y). A current path through a defective wordline can be similarly cut-off.