Abstract: According to one embodiment, a method for storing content addressable memory (CAM) mask values may include storing mask values according to mask size in a mask register set (200). A mask register set (200) may include a number of locations arranged into regions (202, 204, 206 and 208). Each region (202, 204, 206 and 208) can store mask values of a different predetermined size.

Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Abstract: A system (100) may include a content addressable memory (CAM) device (102) and at least two requesting devices (104-0 and 104-n). Requesting devices (104-0 and 104-n) and a CAM device (102) may be connected by at least two communication links (106-0 and 106-n). A CAM device (102) may generate responses to requests, and assign a flow identification value for responses based on a communication link (106-0 and 106-n) on which a corresponding request was received.

Abstract: A method and system for processing wafers is disclosed. According to one embodiment (100) a chuck system (102) may be situated opposite to an input source (104). A chuck system (102) may apply a force (e.g., mechanical and/or electromagnetic) that deforms a substrate (108). Once deformed, essentially all of a substrate (108) may be oriented at a predetermined angle (e.g., 90°) with respect to an input source (104).

Abstract: In the present invention a method is disclosed for communicating within and to the outside of a voice and data network. The voice and data network has applicability to a home or building where existing phone lines are used to interconnect multiple phones and computers within the network. Voice and data modules connect telephones and computers to the existing telephone wiring in a home or building. A link to wide area network allows phone calls to be placed between the network and the Public Service telephone network. All devices connected to the telephone wiring have their own ID and communicate by Tokens in Ethernet technology. This allows Ethernet packets to perform a plurality of communications between a plurality of devices connected to the network under the control of tokens. The communications is accomplished by passing packets containing voice and data signals between phones and computers internal to the network and to an external port to connect to outside of the network.

Abstract: A method of forming an essentially uniform doped insulating layer is disclosed. Variations in a substrate temperature that may result in a dopant gradient within a doped insulating layer can be compensated for by varying a dopant supply rate in a deposition process. One particular embodiment discloses a method of forming a high density plasma phosphosilicate glass having a phosphorous concentration of 8% or greater by weight that varies by no more than about 1% by weight throughout.

Abstract: According to one embodiment, verifying a reticle may include patterning an inspected layer (102-2) according to a reticle pattern, depositing a contrast enhancing layer (104-0) on a patterned layer (102-2), and inspecting a reticle patterned formed in the inspected layer (102-2).

Abstract: According to one embodiment, a shallow trench isolation (STI) method (500) may include forming an etch mask layer over both a first and second substrate side (504). An etch mask layer over a first substrate side (506) may be patterned to form a STI etch mask, and trenches may be etched into a substrate (508). A trench dielectric layer can be formed over a first substrate side (510). An etch mask layer formed over a second substrate side can be etched (512), reducing and/or eliminating stress that may deform a substrate or otherwise adversely affect STI features. A trench dielectric may then be chemically-mechanically polished (step 514).

Abstract: A content addressable memory (CAM) device (100) may include a number of blocks (102-[n?1, n, n+1]) that each generate CAM search results and result compare circuits (104-[n?1, n, n+1] that receive CAM search results from multiple blocks (102-[n?1, n, n?1]), and compare at least a portion of such CAM search results. According to such a comparison result, a compare circuit (104-[n?1, n, n+1]) can generate an output CAM search result for subsequent comparison with CAM search result in another compare circuit (104-[n?1, n, n+1]).

Abstract: A method for cleaning a plasma reactor clamber part (100) may include dipping the chamber part in a solvent (102) that may dissolve a material that has been redistributed on the chamber part by a reactive plasma. A chamber part may then be rinsed (104), ultrasonically cleaned (106) in a ultrasonic cleaning liquid, and then rinsed again with a liquid that may evaporate at a lower temperature than an ultrasonic cleaning liquid (108). A chamber part may then be blown dry (110) and baked (112). In addition, or alternatively, a method may also include plasma cleaning a chamber part (202).

Abstract: According to one embodiment, a programmable logic assembly (200) may include a nonvolatile memory (202) may be coupled to an associated volatile programmable logic device (PLD) (204). Built-in-self-test (BIST) data (208) may be stored in a nonvolatile memory (202) that places the volatile PLD (204) in a self-test configuration. If a volatile PLD (204) passes a self-test, user data (210) may be stored in a nonvolatile memory (202) that places a volatile PLD (204) into a user determined configuration.

Abstract: A method of forming a top oxide layer of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include forming an in situ steam generation (ISSG) top oxide layer 208 from a charge storing dielectric layer 206 by reacting hydrogen and oxygen on a wafer surface (step 102) and depositing a conductive gate layer 210 (step 104). An ISSG top oxide layer 208 may be of higher quality and formed with a smaller thermal budget than conventional approaches.

Abstract: Shallow trench isolation methods and corresponding structures are disclosed. According to one embodiment (900) a nitride layer (1006), having an opening (1014), is formed over a silicon substrate (1002). The portion of the substrate (1002) below the opening (1014) is oxidized to form a substrate consuming rounding oxide layer (1018). The formation of the rounding oxide layer (1018) results in rounded edges in the substrate (1002). An isotropic, or alternatively, an anisotropic rounding oxide etch removes the rounding oxide layer (1018) to expose the substrate (1002). A trench (1026) can be formed by applying a silicon etch using the nitride layer (1006) as an etch mask. The trench (1026) can be subsequently filled with a deposited trench isolation material (1030).

Abstract: A semiconductor device and method of manufacture are provided wherein a contact hole can be formed with increased contact area while maintaining sufficient isolation between an electroconductive layer deposited in the contact hole and an adjacent wire. According to one embodiment (100), a double-layered side-wall insulating layer can be formed within a contact hole (116). The upper (second) side-wall insulating layer (120) can be etched back to expose part of the lower (first) side-wall insulating layer (118) formed in the bottom of the contact hole (116). Subsequently, the exposed portion of the first side-wall insulating layer (118) can be subject to a wet etch to remove the portion of the first side-wall insulating layer (118) at the bottom of the contact hole (116).

Abstract: According to one embodiment (500), a method of depositing an insulating layer to fill constrained spaces on an integrated circuit is disclosed. Gate structures are formed that include sidewall structures (502 and 504). An insulating layer may then be deposited over the gate structures (506). An insulating layer may be deposited by high density plasma CVD to create a silicon dioxide layer with relatively high levels of phosphorous. An insulating layer formed in this manner may fill constrained spaces and may not include a following reflow step. This may allow for a smaller thermal budget and may reduce process complexity and/or cycle time. In the event the insulating layer is substantially phosphosilicate glass (PSG), the formation of a “cap” layer of undoped silicon oxide may be avoided. Without a cap layer, contact holes may be etched through an insulating layer with a single etch step. This may also reduce process complexity and/or cycle time.

Abstract: In the present invention a method and circuit are shown to protect flash memory from data corruption during a rapid power down. A circuit element detect the drop in power voltage and signals that any write operation being performed be switched into a programming phase, and at the same time increase the programming voltage to the flash memory to significantly reduce programming time. If the power drop occurs during an erase phase of a write operation, the erase operation is switched to a program operation using old data to program erased cells. If the power drop occurs during a programming phase of the write operation, the programming phase is continued but at a faster rate.

Abstract: A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step 102), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step 104), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step 106).

Abstract: A phase comparison circuit for generating control voltages for a number of varactors of a phase locked loop (PLL) circuit has been disclosed. According to a particular embodiment, a number of phase difference detection circuits (101, 102 and 103) can be successively activated in response to a set of activation signals to generate output voltage signals (Vtunei). Output voltage signals (Vtunei) can vary according to an elapsed period time, and thus represent a phase difference. Each phase difference detection circuit (101, 102 and 103) can activate a trigger signal (Trg) when an internal voltage signal equals a predetermined value. A main signal (SIG) can be input as an activation signal to a first stage phase difference detection circuit (101). A trigger signal from a first stage phase difference detection circuit (101) can be input as an activation signal to a subsequent stage phase difference detection circuit (102).

Abstract: According to one embodiment, a structure for monitoring a process step may include an etch stop layer (102) formed on a substrate (104) and a trench emulation layer (106) formed over an etch stop layer (102). Monitor trenches (108) may be formed through a trench emulation layer (106) that terminate at an etch stop layer (102). Monitor trenches (108) may have a depth equal to a trench emulation layer (106) thickness. A trench emulation layer (106) thickness may be subject to less variation than a substrate trench depth. A monitor structure (100) may thus be used to monitor features formed by one or more process steps that may vary according to trench depth. Such process steps may include a shallow trench isolation insulator chemical mechanical polishing step. In addition, or alternatively, a monitor structure (100) may be formed on a non-semiconductor-on-insulator (SOI) wafer, but include SOI features, providing a less expensive alternative to monitoring some SOI process steps.

Abstract: According to one embodiment, a content addressable memory (CAM) (100) includes a number of sections (106-1 to 106-i) having data value entries that can be compared to comparand values and/or comparand value portions. Each section (106-1 to 106-i) has an independently configurable width.