Abstract: A reconfigurable datapath (13b), which may be alternatively configured for various debug modes. These modes include a breakpoint mode (20), counter mode (30a-30c), DMA mode (40), and PSA mode (50). Each configuration uses one or more of two bitcell units: a register bitcell unit (60) and a comparator bitcell unit (70). The inputs and interconnections of these bitcell units (60, 70) determine the configuration, and hence the mode, for which they are to be used.

Abstract: A DC-DC converter that does not need a series resistance element on the output side, and can make use of the parasitic resistance of a coil to improve output characteristics and prevent a decrease in efficiency. In switching unit 40, transistors M1 and M2 are turned ON/OFF alternately in correspondence with pulse signal Sp; input voltage Vin is fed intermittently to node ND1; in output filter unit 10, output voltage Vout that is smoothed with coil Le and capacitor Cout is output to terminal Tout. In feedback control unit 100, divided voltage Vo1 obtained by dividing the voltage at node ND1 is compared with reference voltage Vref, and the result of the comparison is integrated to generate control voltage Vc. In PWM modulation unit 30, pulse signal Sp with pulse width controlled is generated according to control voltage Vc and sent to switching unit 40.

Abstract: To reduce the needed bandwidth of video communication system, a portion of the video image that differs from a preceding frame of the video image is predicted from the decompressed audio data with a model operating at both the transmitter and the receiver. The model accuracy is increased and the synchronisation enhanced by reducing the number of degrees of freedom of the model and by making the prediction of the next phoneme in a hierarchical manner.

Abstract: A circuit for widening the stereobase in the reproduction of stereophonic sound signals contains one amplifier (10, 34) each for the stereo signals assigned to the right-hand and left-hand channel. Each amplifier (10, 34) comprises a non-inverting input (16, 36) for the corresponding stereo signal and an inverting input (18, 42) for an output signal fed back via a first resistor (R1, R5) from the amplifier output (20, 40). An ON/OFF connection is provided between the inverting inputs (18, 42) of both amplifiers (10, 34). The connection between the inverting inputs (18, 42) of the two amplifiers (10, 34) is formed by two amplifiers (48, 50) circuited in antiparallel as voltage followers and a second resistor (R8, R9) connected in series with the output of each amplifier (48, 50).

Abstract: A clock generator including a PLL circuit serves to generate an output frequency cycled in a predefined range and containing a desired clock frequency. The PLL circuit contains a voltage-controlled oscillator (18), the oscillating frequency of which is adjustable by means of an analog control voltage to the desired clock frequency in a fixed relationship to a reference frequency applied to the PLL circuit. The clock generator contains a second voltage-controlled oscillator (22), the oscillating frequency of which can be cycled in the predefined range. The second oscillator (22) is configured so that its oscillating frequency can be varied by means of a digital incrementally variable control signal in the predefined range. By varying the output frequency of the clock generator a spreading of its output frequency spectrum is attainable, resulting in a reduction in high-frequency interference by the signal generated by the clock.

Abstract: A cradle for attaching two portable hand-held devices to each other. The cradle holds the devices such that one is substantially atop the other. The cradle has a bottom rim that releasably holds one device. A top rim that releasably holds the other device. Alternative attachment mechanisms for the rims provide either a sliding groove-and-flange type attachment for which the device is specifically designed, and/or a push in type attachment.

Abstract: An improved write drive circuit which includes a discharge circuit added to the base of the bottom transistors of the H-bridge to prevent excessive overshoot and ringing while allowing for higher data rates. The discharge circuit is turned on after the head voltage or current reaches an overshoot condition. In preferred embodiments, the discharge circuit includes variable discharge capability by selecting one or more parallel drive transistors or varying a variable delay in the discharge circuit or any combination of both variables. Both can be controlled by a word written to the disk drive pre-amp over the serial control port.

Abstract: A selectively adjustable impedance boosting circuit for a magneto-resistive head in a disk drive to compensate a frequency pole by introducing a zero in proportion to the resistance of the magneto-resistive element and with selectable circuit parameters to further adjust the pole compensation. The invention includes selectively adjusting the sensitivity of the pole compensation to changes in the resistance of the head, selectively adjusting the peak compensation, and adjusting the frequency of the compensating zero.

Abstract: A method for saturating data in a register (100) is disclosed. The method comprises shifting data contents in the register (100) by a saturation value and setting at least one bit equal to a sign bit (110) on the register (100). The method further comprises storing the shifted contents in a temporary register (160), which (160) has compare bits (180). The method further comprises setting high bits (150) and low bits (140) to a positive value when the compare bits (180) are not equal to the sign bit (110) and the sign bit indicates a positive data word in the register (100). The method further comprises setting the high bits (150) and low bits (140) to a negative value when the compare bits (180) are not equal to the sign bit (110), and the sign bit (110) indicates a negative data word in the register (100). The method further comprises shifting the set data contents in the register (100) by the saturation value and setting at least one bit equal to a least significant bit (102) on the register (100).

Abstract: A linear regulator circuit to regulate an output voltage includes a first current path to conduct a first current, a feedback path to provide feedback to maintain the output voltage at a constant voltage, and a transistor positioned in the first current path to provide the output voltage.

Abstract: A microelectromechanical (MEM) device with an expanded PTFE material over the gap between movable structures to provide electrical connection across the gap and prevent particles from contaminating the gap. A microelectromechanical (MEM) device is also immobilized by placing an expanded PTFE material over the gap between movable structures. The expanded PTFE material can be made stiff during manufacture and then flexible after the manufacturing process is complete. An embodiment of the invention is a MEM device configured as a micro-actuator for a dual-actuator hard disk drive.

Abstract: The circuit configuration for the generation of clock signals for a semiconductor memory (14) that are edge-synchronous with the output signals of a clock generator (16) comprises an input stage (20) to which the output signals of the clock generator (16) are applied. It furthermore contains a phase detector (30) which receives the signals output by the input stage (20) and whose output signals control a voltage-controlled oscillator (34) which supplies the clock signals for the semiconductor memory (14). It also contains a conversion stage (42) which applies signals related to the output signals of the oscillator (34) to the phase detector (30), which controls the oscillator in such a way that the phase difference between the signals reaching it from the input stage (20) and the signals also reaching it from the conversion stage (42) becomes zero. The input stage (20) comprises an amplifier (44) containing a circuit component (62) capable of influencing the signal transit time.

Abstract: A sorting device for a variable-length code containing the following parts: a coding part 43 that converts the length value to a first bit column according to its value, a first shifter 44 that converts the first bit column input from said coding part 43 to a second bit column according to the shift parameters, a second shifter 42 that converts the code value to a third bit column according to the shift parameter, and a register 45 that has the second bit column input from said first shifter 44 and the third bit column input from said second shifter 42, and which outputs only the content of the bit at the position of the third bit column corresponding to the position of the bit indicating the prescribed value “1” of the second bit column.

Abstract: A charge pump-type DC/DC converter comprises n (n≧2) elementary stages, each consisting of a charge pump capacitor and several controllable switches connected thereto, whereby the input voltage of the DC/DC converter is applied to the input of the first stage, both electrodes of the charge pump capacitor of the kth stage are each connectable to one of the controllable switches with the output of the (k−1)th stage, k=2, . . . , n and the output of the nth stage forms the output of the DC/DC converter. The DC/DC converter in accordance with the invention is characterized in that it in addition enables one or more further controllable switches to be connected, via which the electrode of the charge pump capacitor of the nth stage which in the discharge phase is not connected to the output of the converter, to one or more outputs of the 1th stage (1=(n−2), . . .

Abstract: A method to improve the resin sealing reliability in the manufacturing of a wafer-level CSP. The method for manufacturing a semiconductor device of the present invention includes a process that forms wiring 14 and conductive supports 16, which electrically connect electrode pads 10a and corresponding external terminals, on a wafer 10 on which semiconductor elements are formed. In subsequent processes, a groove 18 (preferably V shaped) is formed in the surface of the above-mentioned wafer along the boundary lines of the respective semiconductor elements. Next, the end surfaces of the above-mentioned conductive supports 16 are exposed, and the above-mentioned wafer surface is covered with a resin 19 so that external terminals 20 are arranged on the end surfaces of the conductive supports. In the final process, along the boundary lines of the above-mentioned semiconductor elements, packaged semiconductor devices 32 are obtained by dicing the above-mentioned wafer.

Abstract: A high voltage output stage amplifier that maximizes the output voltage swing when the peak-to-peak output voltage signal is higher than the supply voltage used in the signal conditioning circuits of the amplifier. The amplifier allows the maximum peak-to-peak swing on the output stage by shifting the quiescent voltage of the output stage to the midpoint of the output supply voltage. The shift is accomplished by tapping an offset current at the input of the error integrating stage of the amplifier proportional to the difference in the two power supply voltages.

Abstract: A digital to analog converter includes a network of impedance components having a plurality of nodes having associated voltages. A tap is coupled to one or more associated one of the plurality of nodes to source or sink electrical current relative to the associated node(s). A switching system is operative to couple a selected one of the nodes to an output according to a digital input word and thereby provide an analog voltage corresponding to the digital input.

Abstract: An R-2R type DA converter where the resistance value of the weighting resistors is set to a value calculated by adding the resistance value error to twice the standard resistance value. The resistance value of the terminating resistor (third-value resistor) is set to a value wherein the resistance value error is subtracted from twice the standard resistance value. With these resistance values, when a digital data signal is incremented even if the output voltage immediately before the digital signal is incremented is larger than the output voltage immediately after the digital signal is incremented, the output voltage immediately after the digital signal is incremented will not be excessively large compared to the output voltage immediately after the digital signal is incremented.

Abstract: The purpose of this invention is to ensure an active use of the inverse short-channel effect in the ratio circuit and to guarantee stable operation at low power source voltage. In this ratio circuit, N-channel MOS transistor 12 of CMOS circuit 10 on one side forms the drive element, while P-channel MOS transistor 18 of CMOS circuit 16 on the other side forms the load element. Said N-channel MOS transistor 12 on the drive side and P-channel MOS transistor 16 on the load side have their drain terminals electrically connected to each other through transfer gate 22 made of N-channel MOS transistor. MOS transistor 12 on the drive side has a single channel CHa with the inverse short-channel effect. MOS transistor 18 on the load side has plural, e.g., two, channels CHb1 and CHb2, connected in tandem, each of which displays the inverse short-channel effect.

Abstract: A CMOS bus driver circuit includes an output stage of two complementary MOS transistors and an input stage, where in the connection of the source-drain paths of the MOS transistors (P1, N1) of the input stage a diode (D) is inserted so that the flow of a current in the direction of the MOS transistor (P1) connected to the supply voltage terminal (14) of the input stage is blocked, its cathode being connected to the gate of the one MOS transistor (P2) of the output stage. Connected in parallel to the diode D is the source-drain path of a further MOS transistor (P4), the gate of which is connected to the circuit output (18).