Abstract: A multiprocessor computer system comprises a plurality of processors, wherein each processor includes an execution unit, a program counter, a result buffer containing a plurality of entries, each entry being allocated to hold an output value of an instruction executed by the execution unit, and an operation counter containing an operation count that is incremented at least when an instruction storing an output value to the result buffer is executed by the execution unit. A particular entry allocated in the result buffer for a given output value is selected as a function of the operation count at the time the instruction generating that given output value is executed. Each processor further includes a decoder that extracts a processor identifier from an instruction to be executed that identifies one of the plurality of processors, wherein one or more input values of the instruction are retrieved from the result buffer of the identified processor.

Abstract: A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.

Abstract: A method and system are provided for constructing a program executable by a processor including one or more processing elements for executing threads and a thread scheduler for assigning threads to the processing elements for execution. According to the method, a plurality of threads are provided that each include at least one control flow instruction. From one or more control flow instructions within the plurality of threads, a condition upon which execution of a particular thread depends is determined. In response to the determination, at least one navigation instruction executable by the thread scheduler is created that indicates that the particular thread is to be assigned to one of the processing elements for execution in response to the condition.

Abstract: A data processing system is disclosed, which includes a system unit, a display device for displaying data generated by the system unit, data communication means for communicating display data between the display device and the system unit, a peripheral device, and peripheral communication means for communicating data between the peripheral device and the system unit. In accordance with the present invention, data is communicated between the system unit and the peripheral device via the display device. Data is transferred between the display device and the peripheral device utilizing a wireless communication link, thereby eliminating the problems associated with electrical cables. In a preferred embodiment of the present invention, the wireless communication link includes a first transceiver means located in the display device and a second transceiver means located in a peripheral device. In a first embodiment, the first and second transceiver means comprise infrared transceivers.

Abstract: A data processing system graphical user interface that is customizable to any user-selected color bitmap image is provided. According to the present invention, a user-selected color bitmap image containing a plurality of major objects is imported into the data processing system and set as a scene for the data processing system's graphical user interface. Major objects in the scene are then automatically identified, wherein a major object is one having a plurality of pixels of a selected characteristic. An identified major object is then selected and associated with a set of data, such that when the major object is subsequently selected, a particular data processing system operation is automatically performed utilizing the associated data set.

Abstract: A method and system within a data processing system are disclosed for halting execution of instructions by a processor in response to an enumerated occurrence of a selected combination of internal states within the processor. The processor includes a number of state machines and a means for monitoring the states of the number of state machines. According to the present invention, a selected combination of states of a subset of the state machines is specified. An enumerated occurrence of the selected combination of states of the subset of the state machines is then detected. In response to the enumerated occurrence of the selected combination of states, execution of instructions by the processor is halted such that states of the number of state machines within the processor remain substantially unchanged following the enumerated occurrence of the selected combination of states.

Abstract: A processor and method of predicting a resolution of a speculative branch instruction are described. According to the present invention, a plurality of predicted resolutions of speculative branch instructions and at least one group of bits that indicates a plurality of previous resolutions of branch instructions are stored. A compressed branch history is generated that indicates a number of like previous resolutions within each group of bits. In response to a detection of a speculative branch instruction, a particular predicted resolution among the plurality of predicted resolutions is accessed utilizing the compressed branch history, such that the size of the storage utilized to store the predicted resolutions is reduced as compared to prior art systems.

Abstract: An interlocking disk apparatus for preventing disk slip in a disk stack of a magnetic or optical disk drive is provided. A textured region within the inner diameter of the disks in the disk stack is forced in tight contact with a conformable adjacent surface, such as a spacer ring, clamp plate, and/or hub flange. The textures on the disks penetrate into and/or through the conformal coatings on the adjacent surfaces, resulting in mechanical interlock that inhibits in-plane displacements of the disks from shock and generally improving interfacial contact of the surfaces within the disk stack, thus requiring lower clamping pressures to the disk stack and resulting in greater disk flatness and minimizing disk distortion. Electrostatic Discharge within the disk stack is prevented by diffusing conductive materials into the polymer conformal coating to increase its electrical conductivity.

Abstract: A processor and method for translating a nonphysical address into a physical address are disclosed. A determination is made if a first entry set which could contain a particular entry that associates a selected nonphysical address with a corresponding physical address assigned to a device in the data processing system is stored within a first memory of the data processing system. In response to a determination that the first entry set is not stored in the first memory, a determination is made if a second entry set which could contain the particular entry is stored within the first memory. In response to a determination that the second entry set is stored in the first memory, a search of the second entry set is initiated in order to locate the particular entry. In response to locating the particular entry, the selected nonphysical address is translated to the corresponding physical address utilizing the particular entry.

Abstract: A processor and method for out-of-order execution of instructions are disclosed which fetch a first and a second instruction, wherein the first instruction precedes the second instruction in a program order. A determination is made whether execution of the second instruction is subject to execution of the first instruction. In response to a determination that execution of the second instruction is subject to execution of the first instruction, the second instruction is selectively executed prior to the first instruction in response to a parameter of at least one of the first and second instructions. In one embodiment, the parameter is an execution latency parameter of the first and second instructions.

Abstract: A processor and method of operating a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, a series of guest instructions including at least one unconditional indirect guest branch instruction is stored in memory. In addition, one or more semantic routines that are formed of native instructions and that may be utilized to emulate the series of guest instructions are stored in memory. For each guest instruction in the series of guest instructions, an entry is stored in a multiple-entry queue in order of receipt. The entry includes an indication of a location in memory of at least one semantic routine. In response to the entries in the multiple-entry queue, the series of guest instructions are emulated in the processor by using the entries to access and execute selected ones of the one or more semantic routines.

Abstract: A superscalar uniprocessor that performs concurrent multi-task processing is provided. The processor of the present invention maintains a complete set of program address, memory control and general data registers for each task executing concurrently within the microprocessor, allowing independent control of the program flows. Each set of registers are associated with only one task and are utilized by the memory control and execution units to execute the associated task. The processor includes an instruction fetcher and memory management unit that retrieves an instruction from memory for a given task, as directed by the task's address and control registers, and attaches a task tag to the retrieved instruction that identifies that task. The superscalar processor has a plurality of execution units that can execute a plurality of tasks simultaneously, and a dispatch unit that sends a retrieved instruction and its attached task tag to one of the plurality of execution units for execution.

Abstract: A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register.

Abstract: A network system server that provides password synchronization between a main data store and a plurality of secondary data stores is disclosed. The network system server includes a security server, which is coupled to the main data store, a plurality of clients, which is coupled to the security server for accessing the main data store wherein each client maintains a unique, modifiable password, a password synchronization server, which is coupled to security server and the plurality of secondary data stores, and a password repository, which is coupled to the password synchronization server, that stores the passwords. One of the secondary data stores can retrieve the passwords via the password synchronization server so that each client is able to maintain a single, unique password among the plurality of secondary data stores. Password retrieval is instigated by at least one of the plurality of secondary data stores regardless of the current password status of the secondary data stores.

Abstract: First and second store instructions that target one or more locations in a cache memory are identified. A determination is made whether the cache memory is busy. In response to a determination that the cache memory is busy, the operations specified by the first and second store instructions are merged into a single store operation that subsumes store operations specified by the first and second store instructions. Thereafter, the single store operation is performed.

Abstract: A method and apparatus in a superscalar microprocessor for early completion of floating-point instructions prior to a previous load/store multiple instruction is provided. The microprocessor's load/store execution unit loads or stores data to or from the general purpose registers, and the microprocessor's dispatch unit dispatches instructions to a plurality of execution units, including the load/store execution unit and the floating point execution unit.

Abstract: A computer program product for presenting animated display objects to a user for selection on a graphical user interface of a data processing system is provided. A plurality of animated display objects are simultaneously displayed by a graphical user interface on a display device of the data processing system, thus allowing the user to view all of the plurality of animated display objects and make a selection of one of the plurality of animated display objects. One of the displayed animated display objects is selected, and a multimedia presentation associated with the selected animated display object is played.

Abstract: A number of predefined code blocks are provided from which a sequence or block queue is selected and patterned for a single image line from the pixel image data on which a geometric transformation is to be performed. Once the block queue is generated, it is executed for each image line and the resulting transformed image data is stored in a separate memory or buffer.

Abstract: A network system server that provides password composition checking for a plurality of clients is disclosed. The network system server includes a main data store, a security server, which is coupled to the main data store and the plurality of clients, a password synchronization server, which is coupled to the security server, a plurality of password strength servers, each of which is coupled to the password synchronization server, that provides password integrity among the plurality of clients so that each client maintains a password whose composition is consistent with the network server system. Each of the password strength servers is uniquely programmable with respect to performing password composition checking.

Abstract: The character patterns of all kana (Japanese characters) or kanji (Chinese characters) to be displayed are divided substantially into halves in a horizontal direction (or alternately in a vertical direction) and stored in memory. Image codes corresponding to the divided character patterns thus obtained are assigned thereto, so that an image code is assigned to a corresponding portion of a kana or kanji. Accordingly, when the kana or kanji is displayed, the two image codes (character codes corresponding to the left and right sides of the same character) which are assigned to the above described character patterns are written to addresses of a buffer corresponding to the location on the screen the kana or kanji is to be displayed. Thus, the two portions of the kanji to be displayed are displayed in adjacent areas on the screen of a display device.