Abstract: Disclosed are apparatus and methods for synchronized presentation of analog and digital data by applying a common synchronization scheme to both types of data. Digital data is "streamed" by transferring the data in blocks from a source to a series of memory buffers, where it accumulates for subsequent transfer to an output device driver. The control module responsible for data streaming periodically reports a temporal location within the presentation represented by the data. A supervisory module designates one of the control modules a "master", and periodically compares the values reported by the various other control modules against that reported by the master. If a comparison exceeds a threshold tolerance value associated with each control module, a sync pulse is delivered to that control module, causing it to correct the synchronization mismatch.

Abstract: A graphics display subsystem providing internally timed time-varying properties of display attributes is provided. The graphics display subsystem comprises a display device for displaying consecutive image frames of pixels having a variable display property, and a circuit for transferring image frames to the display device. One or more pixels are selected when a display attribute associated with the one or more pixels is set in an attribute table. The circuit varies, during a selected time interval, the display property of the selected pixels being displayed on the display device. In preferred embodiments, the variable display property is either a stereo image display, an image brightness control, or an image-blending control.

Abstract: A network system server that provides password synchronization between a main data store and a plurality of secondary data stores is disclosed. The network server further includes a security server, which is coupled to the main data store, a plurality of clients, coupled to the security server for accessing the main data store wherein each client maintains a unique, modifiable password, and a password synchronization server, coupled to the security server and the plurality of secondary data stores, that provides password propagation synchronization to each of the secondary data stores from a user associated with one of the plurality of clients so that user is able to maintain a single, unique password among plurality of secondary data stores. The password propagation is imposed on the plurality of secondary data stores regardless of the current password status of the secondary data stores.

Abstract: In a first embodiment, a read detection channel includes a tracking threshold circuit for generating a variable threshold signal and a detection circuit, which is configurable in a number of diverse configurations that each correspond to one of the multiple diverse data formats. In addition, the first embodiment of the read detection channel includes a configuration circuit that automatically selects one of the configurations of the data detection circuit in response to a detection of a format of the input data stream. The first embodiment of the read detection channel permits data bits encoded in multiple diverse data formats to be decoded utilizing a single configurable read detection channel. In a second embodiment, the configurable read detection channel includes a tracking threshold circuit that can be configured to generate a threshold output signal in response to an input signal or in response to the input signal and a phase error signal.

Abstract: A method and system for dynamically reconfiguring a cluster of computer systems are disclosed. In accordance with the present invention, a first configuration file is provided at a plurality of computer systems within a cluster that specifies a current configuration of the cluster. A second configuration file is created at each of the plurality of computer systems that specifies a modified configuration of the cluster. The modified configuration is then verified. In response to the verification, the cluster is operated utilizing the modified configuration. In accordance with one embodiment, the dynamic reconfiguration of the cluster can include a reconfiguration of the cluster topology or resources.

Abstract: A superscalar processor and method for executing fixed-point instructions within a superscalar processor are disclosed. The superscalar processor has a memory and multiple execution units, including a fixed point execution unit (FXU) and a non-fixed point execution unit (non-FXU). According to the present invention, a set of instructions to be executed are fetched from among a number of instructions stored within memory. A determination is then made if n instructions, the maximum number possible, can be dispatched to the multiple execution units during a first processor cycle if fixed point arithmetic and logical instructions are dispatched only to the FXU. If so, n instructions are dispatched to the multiple execution units for execution.

Abstract: A method and system are disclosed for tracking the allocation of resources within a processor having multiple execution units which support speculative execution of instructions. The processor includes a resource counter including a first counter and a second counter and a number of resources, wherein one or more of the resources are allocated to each of a number of instructions dispatched for execution to the execution units. In response to dispatching an instruction among the plurality of instructions to one of the execution units for execution, the first counter is incremented once for each of the resources allocated to the instruction, and if the instruction is a first instruction within a speculative execution path, the second counter is loaded with a value of the first counter prior to incrementing the first counter.

Abstract: A method and system of enhancing memory performance in a data processing system are provided. The data processing system may include a processor having an on-board first-level cache, a second-level cache coupled to the processor, a system bus coupled to the processor, and a main memory coupled to the system bus. When a memory request is received for a cache line at the first-level cache, a determination is made if the memory request is initiated by a store operation. If the memory request results in a hit in the first-level cache and a determination is made that the memory request is store-initiated, a corresponding cache line in a second-level cache is invalidated.

Abstract: A floating point numbers load-store unit includes a translator for converting between the single-precision and double-precision representations, and Special-Case logic for providing Special-Case signals when a store is being performed on zero, infinity, or NaN. A store-float-double instruction is executed by concatenating a suffix to the mantissa in the single-precision floating-point register and replacing the high-order bit of the exponent with a prefix selected as a function of the high-order bit, wherein the resulting mantissa and exponent form a double-precision floating-point number that is then stored to memory. A load-float-double instruction is executed by dropping the suffix from the mantissa of the double-precision floating-point number in memory, and replacing the prefix with the high-order bit, wherein the resulting mantissa and exponent form a single-precision floating-point number that is then loaded into the single-precision floating-point register.

Abstract: A method and apparatus for magnetic treatment of liquids. The method involves a single step of flowing the liquids through a plurality of magnetic fields, the magnetic fields alternating in field direction and progressively decreasing in field strength.

Abstract: A write-back cache memory and method for maintaining coherency within a write-back cache memory are disclosed. The write-back cache memory includes a number of cache lines for storing data associated with addresses within an associated memory. Each of the cache lines comprises multiple byte sets. The write-back cache memory also includes coherency indicia for identifying each byte set among the multiple byte sets within a cache line which contains data that differs from data stored in corresponding addresses within the associated memory. The write-back cache memory further includes cache control logic, which, upon replacement of a particular cache line within the write-back cache memory, writes only identified byte sets to the associated memory, such that memory accesses and bus utilization are minimized.

Abstract: A cache coherence network for transferring coherence messages between processor caches in a multiprocessor data processing system is provided. The network includes a plurality of processor caches associated with a plurality of processors, and a binary logic tree circuit which can separately adapt each branch of the tree from a broadcast configuration during low levels of coherence traffic to a ring configuration during high levels of coherence traffic. A cache snoop-in input receives coherence messages and a snoop-out output outputs, at the most, one coherence message per current cycle of the network timing. A forward signal on a forward output indicates that the associated cache is outputting a message on snoop-out during the current cycle. A cache outputs received messages in a queue on the snoop-out output, after determining any response message based on the received message. The binary logic tree circuit has a plurality of binary nodes connected in a binary tree structure.

Abstract: A method and data processing system are disclosed for controlling the access of a plurality users to a computer system connectable over a network to a plurality of computers. The data processing system has facilities for restricting user access to the data processing system which includes a user authentication procedure in which at logon a user's identity is compared with a list of authorized users. In addition, the data processing system has a system-wide profile referenced by all users of the system at logon and temporary access control facilities for temporarily preventing access to the system by a normally authorized user or users. The temporary access control facilities allow a privileged user of the computer system to create a list of temporarily unauthorized users that is referenced by the system-wide profile at logon.

Abstract: An improved file system, file system object and method for customizing a file system object within a data processing system are disclosed. The data processing system executes an operating system and includes a storage media having contents organized according to a file system. According to the present invention, a file system object is stored within the storage media which comprises object data, a procedure, and a node that contains a number of attributes of the file system object. The attributes of the file system object contained within the node include an object data location indicator which indicates one or more locations of the object data within the storage media and a procedure location indicator which indicates one or more locations of portions of the procedure within the storage media.

Abstract: A high performance dynamic logic compatible transparent latch is provided. The latch comprises a first switchable invertor circuit, a second invertor circuit, and a third switchable invertor circuit. The first invertor, having a data input, a clock input and an output, is enabled by a first phase of an input clock and is disabled by a second phase of the input clock. The second invertor has an input connected to the first invertor output. The third invertor has a clock input, and is enabled by the second phase of the input clock and disabled by the first phase of the input clock, and further has an input connected to the second invertor output and an output connected to the second invertor input.

Abstract: A device for aligning the radix point of an unaligned binary result of a floating point operation to a normalized or denormalized position is provided. The device comprises an alignment circuit that produces a shift alignment vector indicating the position of the most significant bit of the unaligned result that is set, when a normalized result is required, and that produces a shift alignment vector indicating the position of a bit of the unaligned result having the weight of a minimum allowable exponent for a given format, when a denormalized result is required. A shift register responsive to the alignment circuit shifts the unaligned result by the number of bits indicated by the shift alignment vector.

Abstract: An automated method and system for designing an integrated circuit are disclosed which construct an initial substrate layout of the integrated circuit in response to receipt of a high-level functional description of an integrated circuit. The initial substrate layout, which includes a number of subcircuits electrically connected by a number of interconnects, is constructed based upon estimated timing characteristics of the subcircuits. Next, particular subcircuits are arranged to optimize performance of the substrate layout of the integrated circuit. Performance characteristics of the substrate layout, including timing characteristics of the number of subcircuits and resistive and capacitive characteristics of the number of interconnects, are then determined. In response to a determination of the performance characteristics of the substrate layout, operating power levels of selected subcircuits and resistances of selected interconnects are adjusted to optimize performance of the substrate layout.

Abstract: A method of and system for implementing dynamic translucent windows in a graphical user interface. Each translucent window has associated therewith a foreground buffer and a background buffer. Whenever a translucent window is updated, the system, starting with the lowest z-order updated translucent window, combines the updated translucent window's foreground and background buffers into a translucent image. If the translucent image is in a clip region, the system displays the portion of the translucent image in the clip region and turns off the update marker. If the translucent image is in a deferred clip region, the system copies the portion of the translucent image in any deferred clip region into the background buffer or buffers of the translucent window or windows that define the deferred clip region and marks the translucent window updated.

Abstract: A method and apparatus for supporting speculative execution of count and link register modifying instructions in a microprocessor is provided. The apparatus includes a queue of rename buffers storing count/link register operand data resulting from speculatively executed instructions that modify a count/link register. The queue contains a set of control buffers, wherein each control buffer contains control bits associated with a rename buffer, the control bits including an instruction identifier tag identifying a speculatively executed instruction, the operand data of the speculatively executed instruction being stored in the associated rename buffer, and an available bit indicating when the operand data no longer needs to be stored in the associated rename buffer.

Abstract: A method and system are disclosed for managing the deallocation of a rename buffer allocated to an update instruction within a processor. The processor has a number of rename buffers for temporarily storing information associated with instructions executed by the processor, a number of registers, and a memory. According to the present invention, an update instruction is dispatched to the processor for execution. A particular rename buffer is then allocated to the update instruction. An effective address is generated for the update instruction, wherein the effective address specifies an address within the memory to be accessed by the update instruction. Next, the effective address is stored within the particular rename buffer. Prior to completion of the access to the effective address within memory, the effective address is transferred from the particular rename buffer to a particular one of the number of registers.