Abstract: Systems and methods for estimating IQ imbalance in a communication system are provided. In various embodiments, a device is configured to perform a self-characterization. The self-characterization is performed over an RF loopback circuit. In some embodiments, a probe is transmitted over the RF loopback circuit. The probe uses a frequency offset such that an image related to one IQ imbalance is separated from an image related to another IQ imbalance. An imbalance estimate is calculated based on processing of the probe.

Abstract: According to various embodiments of the disclosed method and apparatus, nodes on a network are programmed to generate a probe transmission in response to a request from the node that will be receiving the probe. The receiving node may generate a probe request that specifies a plurality of parameters, such as a modulation profile for the probe; the payload content of the probe; the number of times to transmit the probe; a number of symbols for the payload of the probe; a preamble type for the probe; a cyclic-prefix length for the payload of the probe; a transmit power for the probe; and a transmit power scaling factor for the payload of the probe.

Abstract: A system that transmits data over multiple networks receives data packets at a client node and forms a plurality of data aggregates from the data packets. The system then sends a request for a duplicate transmission to a coordinator node on a first network. In response to the request, the system receives a first transmission slot on the first network and a second transmission slot on a second network for transmission of the data aggregates. The system then splits the data aggregates among the first transmission slot and the second transmission slot and transmits the data aggregates on the first transmission slot and the second transmission slot.

Abstract: Systems and methods for providing a mechanism by which digital signals can be converted to analog signals with an efficient structure that reduces the number of filters required by providing a mechanism for cancelling images that would otherwise be generated. By adjusting three parameters in the system, a selection can be made as to whether to generate upper sidebands, lower sidebands and in which direction the envelope of the output from the system will be skewed.

Abstract: Techniques for accelerated processing associated with analog to digital signal conversion are disclosed. Accelerated processing is provided for sample-and-hold and track-and-hold circuits used with analog to digital converters in various embodiments. An abbreviated sampling state, an abbreviated reset state, or both are employed in various embodiments. By accelerating processing so as to avoid the need for waiting for a signal to settle within a predetermined tolerance, errors of different types may be incurred. Such errors are determined during calibration and stored for future retrieval and error compensation. Techniques for online and offline calibration are disclosed, whereby calibration may or may not impact normal signal conversion processing. Techniques disclosed herein find broad applicability in analog to digital conversion and yield faster processing in a variety of contexts.

Abstract: Methods and apparatus for capacitive voltage division are provided, an example apparatus having an input and an output and including a first switched capacitor circuit. In some embodiments, the capacitive voltage divider includes first and second MOSFETs. A first capacitor is coupled between the drain of the first MOSFET and the input to the capacitive voltage divider. A first circuit coupled to the drain of the first MOSFET is configured to pull down the drain of the first MOSFET and thus apply a reverse bias to a first junction diode internal to the first MOSFET between the drain and the bulk of the first MOSFET. A second capacitor is coupled between the source of the first MOSFET and the drain of the second MOSFET. A second circuit is configured to reverse bias a second junction diode between the drain and bulk of the second MOSFET.

Abstract: A communications system and method comprises the steps of performing at least one Layer 2 transaction comprising a plurality of wave cycles, each Layer 2 transaction including performing a first wave cycle, concatenating the received first responses from each of the one or more nodes, and performing a second wave cycle. The first wave cycle includes broadcasting a first request from a network coordinator to a plurality of nodes connected to a coordinated network, and receiving a first response from one or more of the nodes indicating that the nodes have opted to participate in a next subsequent wave cycle. The second wave cycle includes transmitting a subsequent request from the network coordinator to each of the one or more nodes based upon the concatenated first responses.

Abstract: A broadband tuner includes a tracking filter with calibration to compensate for component errors and drift. The filters use off-die inductors that are preferably within a system-in-package (SIP) with other critical tuner components, which produces a highly integrated tuner front end with high Q filters within a single package. High voltage varactors with a large tuning range can be used for variable capacitors. The integration of the tuner into a SIP allows the tuner design to be optimized for cost and performance while keeping the critical RF layout requirements within the tuner. A configurable tuner front end enables modes for low noise, high linearity, good input return loss (S11) across the entire RF band, and applying a test tone in the calibration mode. The switchable mode enables the tuner to be effective during weak terrestrial reception, strong terrestrial reception, and connection to a cable plant.

Abstract: A satellite interference canceling system cancels the interference between two or more signals received by a satellite receiver. The signals can be two signals experiencing cross polarization interference or signals that experience interference from other satellite signals. Gain and phase are applied to the received signals and then combined with the other signals to result in cancellation by subtraction. The gain and phase values needed to cancel the interference are derived from measurements of carrier-to-noise ratio (C/N) as an indication of the interference level. The C/N can be measured in the set-top box indoor unit. Coherency restoration is performed in receivers that downconvert the signals before performing interference cancellation.

Abstract: An outdoor satellite receiving unit (ODU) receives several independent satellite signals, selects two signals with a switch matrix, downconverts the two signals to a bandstacked signal with a high and a low band signal, and outputs the bandstacked signal on the same cable to receiver units. Several satellite signals can be selected in groups of two or more and output to independent receiver units. Signal selecting is performed at the received radio frequency (RF) and bandstacking is performed with a single downconversion step to an intermediate frequency (IF). Channel stacking on the same cable of more than two channels from several satellites can be achieved by using frequency agile downconverters and bandpass filters prior to combining at the IF output. A slow transitioning switch minimizes signal disturbances when switching and maintains input impedance at a constant value.

Abstract: An efficient algorithm is described for use with OFDM receivers that characterizes the impulse response of a communication channel using frequency domain techniques that reduce computational and memory requirements, relative to time-domain cross-correlation methods, without sacrificing algorithm performance. An FFT engine is used to transform a time domain input sequence, the transformed sequence is multiplied by the conjugate of the expected sequence, the product of several sequences is averaged, then the FFT engine transforms the average back to a time domain sequence, the magnitude of which is the impulse response of the channel.

Abstract: In an orthogonal frequency division multiplex (OFDM) communication network, a node transmits an echo profile probe to other nodes in the network. The echo profile probe is a message that allows characterization of the unique echo profile through the communication channel between each node pair. The echo profile is used to calculate the cyclic prefix length needed for optimum communication from one node to the other.

Abstract: A node forms a network by scanning for an existing network. If an existing network is not found, the node operates as a network controller node of the first network and admits at least one client node to the first network. As a network controller node, the node designates one of the client nodes as a scout node. The scout node removes itself from the first network and scans for a second network. If the scout node does not return to the first network after a predetermined time, it is assumed that the scout node has found a second network. The network controller node of the first network then designates the remaining client nodes as scout nodes, and then joins the second network as a client node. Therefore, multiple networks are avoided.

Abstract: Methods and apparatus for capacitive voltage division are provided, an example apparatus having an input and an output and including a first switched capacitor circuit. In some embodiments, the capacitive voltage divider includes first and second MOSFETs. A first capacitor is coupled between the drain of the first MOSFET and the input to the capacitive voltage divider. A first circuit coupled to the drain of the first MOSFET is configured to pull down the drain of the first MOSFET and thus apply a reverse bias to a first junction diode internal to the first MOSFET between the drain and the bulk of the first MOSFET. A second capacitor is coupled between the source of the first MOSFET and the drain of the second MOSFET. A second circuit is configured to reverse bias a second junction diode between the drain and bulk of the second MOSFET.

Abstract: Various embodiments of methods and systems for pausing and shaping data flow while supporting both parameterized and prioritized Quality of Service are disclosed. In some embodiments, a system for pausing and shaping data flow comprises an input buffer, a first pause controller coupled to the input buffer and an output buffer for flow control messages. Various embodiments also include a hop-1 buffer coupled to the input buffer and a hop-2 buffer comprising a plurality of queues coupled to the hop-1 buffer. Additionally, in some embodiments, a second pause controller is coupled to the queues. The second pause controller selects a queue or queues that will cause a pause to be generated based on a predetermined condition. A two-hop process controller controls the data packet flow from the input buffer to the hop-1 buffer and from the hop-1 buffer to the hop-2 queues based on packet classification.

Abstract: Several local IEEE1394 buses are bridged together over a second bus type to create a global bus wherein each local bus node is able to address nodes across the global bus without the local nodes being aware of the bridging operation. A bridging device operates by translating local bus node addresses to a global bus for communication over the second bus type. Alternatively, the local bus node identification process is controlled by the bridging device operating as the root node to cause the local nodes to be identified with a node address that is unique for the global network. The second bus type operates as a backbone for the global network and can be any type of communication bus or network with capability to transport the local bus traffic. The bridging devices that interface the local IEEE1394 buses to the backbone contain portals specific to each bus type that can communicate data between the dissimilar buses.

Abstract: In-phase (I) and quadrature-phase (Q) signals are corrected for both amplitude and phase imbalances by passing the I and Q signals successively through a first amplitude correction stage, a sum-difference stage, and a second amplitude correction stage. The first amplitude correction stage balances the signal levels of the I and Q signals. The sum-difference stage produce a sum of the input I and Q signals, and a difference of the input I and Q signals, resulting in ideal quadrature in the outputs produced. The second amplitude correction stage corrects the amplitude differences from the sum-difference stage. Circuit configurations are used that minimize errors produced by the signal processing stages.

Abstract: A broadband cable network (“BCN”) for determining a common bit-loading modulation scheme for communicating between a plurality of nodes in the BCN is disclosed. The BCN may include a transmitting node within the plurality of nodes where the transmitting node is capable of sending a probe signal to the plurality of nodes, and at least one receiving node within the plurality of nodes in signal communication with the transmitting node. The at least one receiving node is capable of transmitting a first response signal in response to receiving the probe signal. The first response signal includes a first bit-loading modulation scheme determined by the at least one receiving node. The transmitting node is further capable of determining the common bit-loading modulation scheme from the first response signal.

Abstract: A tunable duplexer using voltage-controlled varactors is presented. The center frequency, the pass band, and the stop band are each tunable to meet system requirements. A calibration circuit driving digital to analog converters produces the necessary voltages used in the resonant circuits. The tunable duplexer can be fabricated on a single silicon chip. On-chip transformers can be used to reduce the voltage level of signals in the filters to improve the linearity of the duplexer.

Abstract: Multiple channels of received data are processed by a multiple channel demodulation and error correction decoding engine. The statistical uncertainty of processing channels with an iterative decoder are averaged across all the channels to reduce the total processing power required of the decoding engine compared to processing each channel with a separate engine. A set of input buffers holds blocks of data for each channel needing decoding. A quality measure is computed on each input block to set the priority and iteration allocation of decoding in the common decoder. The input RF signal is digitized by a broadband tuner that processes some or all of the channels to feed the multiple channel demodulator and decoder. Multiple decoded video data streams are output.