Abstract: A method of fabricating dynamic random access memory. A conductive layer, a metal silicide layer, a first cap layer and a second cap layer are formed and patterned to form gate structures on the substrate. A first oxide layer is formed over the sidewalls of the metal silicide layer and the conductive layer as well as over the exposed substrate. First spacers are formed on the sidewalls of the gate structures. A second oxide layer is formed over the substrate. Second spacers are formed on the sidewalls of the second oxide layer. A third oxide layer is formed over the substrate. The second spacers, the second oxide layer and a portion of the first oxide layer are removed to expose a portion of the substrate. Contact pads that expose the second cap layer and a portion of the first spacers are formed, and then a first dielectric layer is formed over the entire substrate. Source/drain regions are formed on each side of the third oxide layer in the substrate.

Abstract: A fabrication process for a polysilicon gate is described in which a silicon dioxide layer of various thicknesses is formed on the substrate and on the polysilicon gate with an overlying anti-reflection layer. The silicon dioxide layer is removed with enough silicon dioxide layer remaining to cover the sidewalls of the polysilicon gate and the silicon substrate before the removal of the anti-reflection layer. The sidewalls of the polysilicon gate and the silicon substrate are thus simultaneously protected during the removal of the anti-reflection layer.

Abstract: A fabrication method for a capacitor is proposed, beginning with a semiconductor substrate having a bit line and a planarized first dielectric layer formed thereon. A first silicon nitride layer is formed on the first dielectric layer, followed by forming in sequence a second dielectric layer and a second silicon nitride layer on the first silicon nitride layer. A photolithography and etching process is performed to form an opening in the second dielectric layer and the second silicon nitride layer. A conducting spacer is formed on a sidewall of the opening. With the spacer serving as a mask, the first silicon nitride layer and the first dielectric layer are etched to form a terminal contact opening. A conducting layer is then formed to cover the second silicon nitride layer and to fill the terminal contact opening, while the conducting layer on the second silicon nitride layer is removed by etching back.

Abstract: A method for fabricating a bottom electrode is provided. In this method a dielectric layer is formed on a substrate having a source/drain region. A via hole is formed in the dielectric layer to expose the source/drain region. A patterned, doped polysilicon layer is formed on the dielectric layer and fills the via hole, wherein the cross-section of the patterned doped polysilicon layer is arced or polygonal. The surface of the patterned polysilicon layer is transformed into an amorphous silicon layer. A hemispherical-grain layer is formed on the amorphous silicon layer.

Abstract: A method for fabricating a DRAM with a silicide layer formed on a gate of a MOS transistor in a memory region is provided. The method not only forms a first silicide layer on a first MOS transistor at the periphery region as a conventional structure but also forms a second silicide layer on a gate of a second MOS transistor, at the memory region. The second silicide layer is formed on a polysilicon layer before the polysilicon is patterned to form a gate so that the gate includes the second silicide layer on it top. An insulating layer is also formed over the substrate before the polysilicon is patterned so that the insulating layer serve as a mask when an interchangeable source/drain region of the second MOS transistor is formed.

Abstract: A method is described for manufacturing a shallow trench isolation. The method comprises the steps of providing a substrate having a pad oxide layer, a mask layer and a trench, wherein the trench penetrates through the mask layer and the pad oxide layer and into the substrate. A liner oxide layer is formed on a portion of the sidewall of the trench in the substrate. A silicon layer is formed in the trench with a same surface level as the interface between the substrate and the pad oxide layer and an insulating layer is formed on the silicon layer.

Abstract: A method of forming a dynamic random access memory cell such that the gate conductive layer, the bit line contact, the node contact, the bit line and the node contact plug are all formed using self-aligned processes. By employing the self-aligned method of forming DRAM cell, isolation structures are no longer etched in the process of forming the node contact opening. In addition, the aspect ratio of the node contact opening is reduced and processing window is thereby widened.

Abstract: A dielectric layer in a dual-damascene interconnect is described. A dual-damascene interconnect structure is formed on a substrate. The dual-damascene interconnect structure has a first dielectric layer formed over the substrate, a second dielectric layer formed on the first dielectric layer, a first wire penetrating through the second dielectric layer and a second wire. The second wire penetrates through the second dielectric layer and is electrically coupled to the substrate. The second dielectric layer is removed. A barrier cap layer is formed conformally over the substrate. A third dielectric layer is formed on the barrier cap layer and an air gap is formed in a space enclosed by the third dielectric layer, the first and the second wires. A fourth dielectric layer is formed on the third dielectric layer. A planarizing process is performed to planarize the fourth dielectric layer.

Abstract: A method for forming a metallic reflecting layer in a semiconductor photodiode including a CMOS photodiode to enhance the sensitivity by filling a trench formed in the isolation next to the depletion region of the semiconductor photodiode with high reflectivity metal. The metal filled in the trench is used as a metallic reflecting layer to increase the number of photons reaching the depletion region by reflecting part of the aslope incident photons. An insulator is formed on the top of the metallic reflecting layer to electrically insulate the metallic reflecting layer from other conducting device formed by the follow-up process.

Abstract: A method for forming a metal plug is provided. The method is used to form a metal plug without a hole on a glue/barrier layer within a trench when the glue/barrier layer has been formed for a while. A substrate with a trench therein and a glue/barrier layer formed conformal to the profile of the substrate is provided. A post-treatment is performed on the glue/barrier layer to prevent moisture absorption and to make the glue/barrier become dense. The post-treatment comprises a plasma treatment or a deep UV plus laser treatment. After performing the post-treatment step, a metal layer is formed on the glue/barrier layer at least to fill in the trench. The metal layer other than that filling the trench is removed to form a metal plug.

Abstract: A fabrication method for shallow trench isolation (STI) is briefly described as follows. A substrate is provided with a patterned mask layer and pad oxide layer formed thereon, so that a first opening, which exposes a part of the substrate, is formed. A shallow trench is then formed in the substrate, followed by filling the shallow trench with a first insulating layer, wherein the surface of the first insulating layer is lower than the surface of the substrate, and a part of the substrate forming the sidewall of the shallow trench is exposed. A part of the mask layer and pad oxide layer is removed to enlarge the first opening, so that a second opening, which exposes a part of the substrate, is formed. A doped region is formed on the exposed part of the substrate, while the second opening and the shallow trench are filled with a second insulating layer. Finally, the mask layer and the pad oxide layer are removed in sequence to complete the manufacture of the STI.

Abstract: A Method for forming a dynamic random access memory device with an ultra-short channel and an ultra-shallow junction is described in the invention. In the invention, the spacer is used as a mask to define the channel length of the device, so that the channel length of the device is not limited by the resolution of the photolithography process, and the performance of the device is improved thereby. Furthermore, an inversion layer serves as a junction to reduce the electric field; thus, the reliability of the device is increased.

Abstract: A method of manufacturing multiple metallic layered embedded ROM. A substrate has a memory cell region and a peripheral circuit region. A first gate and a first source/drain region are formed in the memory cell region. A second gate and a second source/drain region are formed in the peripheral circuit region. A first dielectric layer is formed over the substrate. A first contact is formed in the first dielectric layer in the periphery circuit region. A first patterned metallic layer that couple electrically with the first contact is formed in the peripheral circuit region. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer in the memory cell region is removed to form a remaining second dielectric layer having a sloping sidewall surrounds a periphery of the memory cell region. A via hole is formed in the second dielectric layer in the peripheral circuit region and a second contact opening is formed in the first dielectric layer in the memory cell region.

Abstract: A method for fabricating a double-cylinder capacitor is provided. The double-cylinder capacitor has a storage electrode having dual, concentric cylinder structures. The dielectric layer and the top electrode are formed in sequence over the bottom electrode. The storage area is thus enlarged by the double-cylinder capacitor of the invention. Thus, the capacitance of the capacitor can be effectively increased.

Abstract: A method of fabricating a lower electrode of a capacitor. A sacrificial multilayer is formed on a semiconductor layer. The sacrificial multi-layer is a stack of alternating first and second sacrificial layers. A patterned first mask layer having a first opening above a conductive plug in the semiconductor substrate is formed on the sacrificial multi-layer. A planar spacer is formed on the sidewall of the first opening. A second mask layer is formed to fill the first opening. The planar spacer and the sacrificial multi-layer thereunder are anisotropically etched until the semiconductor substrate is exposed to form a second opening while using the first mask layer and second mask layer as a mask. The first sacrificial layers exposed by the second opening are isotropically etched to form a plurality of recesses. The second opening and the recesses are filled with a conductive material layer. Finally, the first mask layer, second mask layer, and sacrificial multi-layer are removed.

Abstract: A multiple box case for housing audio equipment in both a transport and an operating mode is disclosed. An upper box has six latches extending downward to engage two continuous slider members fastened to a lower box to secure the case in the transport or closed mode. In an open or operating position, the upper box is cantilevered over the rear of the lower box and four of the six latches engage the two slider members in an operator preferred one of a plurality of continuously selectable positions. A safety stop bolt is installed in each slider member so as to preclude unstable positioning of the upper box.

Abstract: A method of forming buried bit lines. A silicon-on-insulator (SOI) substrate includes a silicon base layer, a first insulation layer and an epitaxial silicon layer. A shallow trench isolation (STI) layer that contacts the first insulation layer is formed in the epitaxial silicon layer. A trench that penetrates the STI layer and runs deep into the first insulation layer is formed. A buried bit line is formed inside the trench such that the top surface of the buried bit line is located between the upper and the lower surface of the STI layer. A second insulation layer is next formed over the buried bit line such that the top surface of the second insulation layer is at the same level as the top surface of the epitaxial silicon layer. A plurality of word lines and a plurality of source/drain regions are formed over the substrate and in the epitaxial silicon layer.

Abstract: A method for integrating a high-voltage device and a low-voltage device. A substrate has a high-voltage device region, a low-voltage device region and a scribe region, wherein a patterned insulating layer is formed on the substrate in the high-voltage device region and the scribe region. A grade region is formed in the substrate exposed by the patterned insulating layer in the high-voltage device region. A plurality of protuberances is formed on the substrate exposed by the patterned insulating layer in the high-voltage device region and in the scribe region. The patterned insulating layer and the protuberances are removed to form recesses at locations of the protuberances. A first gate structure and a second gate structure are respectively formed on the substrate between the grade region in the high-voltage device region and on the substrate in the low-voltage device region while using the recesses as alignment marks.

Abstract: A method of spin-on-glass planarization. A spin-on-glass layer is formed on a substrate. An accuflo layer with a better fluidity than the spin-on-glass material is formed on the spin-on-glass layer. The accuflo layer and the spin-on-glass layer are etched back by two etching steps with different etching rate. The accuflo layer after being etched is stripped. A dielectric layer is formed.

Abstract: A plumb system for construction projects having a laser module embedded within includes a spring or the like device acting as a connecting device to a tripod or the like apparatus for projecting a vertical laser beam to a vertical end point, from the floor to a certain top point. Conversely, a spring or the like device mounted to the opposite end of the laser module of the plumb can be mounted to a certain high point for projecting a top to bottom laser beam for determining an end point at the floor. An optional horizontal base designed to horizontally receive the plumb for projecting a horizontal laser beam. A horizontal level indicator mounted onto the horizontal base can ensure a true horizontal plane. An optional self standing horizontal block can be used to determine the intermediate points of the horizontal laser beam.