Abstract: A method for forming a shallow trench isolation structure. A pad oxide layer is formed over a substrate. A hard mask layer is formed over the pad oxide layer. A portion of the hard mask layer, the pad oxide layer and the substrate is removed to form a trench in the substrate. Insulation material is deposited into the trench to form an insulation plug. The hard mask layer is removed to expose the sidewalls of the insulation plug. Spacers are formed on the exposed sidewalls of the insulation plug. Ions are implanted into the substrate. The pad oxide layer, the spacers and a portion of the insulation plug are removed. Finally, a gate oxide layer thicker in region around the edge of the insulation plug is formed over the substrate by oxidation.

Abstract: A method of fabricating a dynamic random-access memory (DRAM) device integrates a shallow trench isolation (STI) process and a storage node process into the fabrication of the DRAM device. With a bit line over capacitor (BOC) structure, the capacitor is laid out in parts of the shallow trench isolation structure to increase the surface area of the storage node by using the trench. During the fabrication of the capacitor, a stacked plug used to connect the bit line is formed. The stacked plug used as the interconnection in the circuit region is also formed. An insulating layer is formed to cover the capacitor, and an opening is formed therein to expose the stacked plug. A bit line and an interconnection are formed on the insulating layer to connect with a conducting layer which is located in the stacked plug and contacted with the source/drain regions.

Abstract: A dual damascene process is provided. A dielectric layer is formed on a substrate having a conductive region. The dielectric layer is selectively doped to form a doped region aligned over the conductive region. The doped region, the dielectric layer underlying the doped region, and another part of the undoped dielectric layer are etched until the conductive region is exposed, so that a dual damascene opening exposing the conductive region and a trench are formed, wherein the dual damascene opening comprising a upper trench and a lower via hole. The dual damascene opening and the trench are filled with a conductive layer.

Abstract: A method to form a better quality of an alignment pattern includes several steps, first starts from forming a polysilicon layer on a semiconductor substrate. Next, most of a central portion of the polysilicon layer is removed to expose the substrate. Then, an oxide layer is formed over the substrate and is patterned to form an opening, which exposes the substrate. A W layer is deposited over the substrate and is planarized by WCMP process to form a W plug inside the opening. A metal layer is formed over the substrate. The alignment mark pattern is formed on the metal layer.