Abstract: A nano-pattern lithographic fabrication apparatus for fabricating a fine pattern using a pulled micro-pipette is disclosed. This apparatus includes a container for receiving a certain solution therein, a container controlling unit for controlling the movement of the container and an ejection of the solution filled in the container, a sample moving unit for supporting and moving the sample, a detector for detecting a distance between the container controlling unit and the sample moving unit, and a controlling unit for receiving a detection signal from the detector and controlling the movement of the container and the sample moving unit and a distance therebetween.

Abstract: An X-ray computer tomography scanning system for imaging the internal structure of a human being including a source that projects a substantially conically shaped X-ray beam along a path on to a subject such that at least a portion of said beam is transmitted through said subject and a detector array that detects the portion of the beam transmitted through the subject and operative to generate electronic signals in response to the beam transmitted through the subject that projects on to said detector array. The system also including a patient support structure for supporting the subject and rotating said subject about an axis intersecting with and substantially perpendicular to the path of the beam, wherein said subject is constrained such that the subject remains in the path of said beam and an airbag restraining mechanism attached to the support structure for holding the subject in its position.

Abstract: The FPGA array in the Simulation system is provided on the motherboard through a particular board interconnect structure to provide easy expandability and maximize packaging density with a single PCB design. Each chip may have up to eight sets of interconnections, where the interconnections are arranged according to adjacent direct-neighbor interconnects (i.e., N[73:0], S[73:0], W[73:0], E[73:0]), and one-hope neighbor interconnects (i.e., NH[27:0], SH[27:0], XH[36:0], XH[72:37]), excluding the local bus connections, within a single board and across different boards. Each chip is capable of being interconnected directly to adjacent neighbor chips, or in one hop to a non-adjacent chip located above, below, left, and right. In the X direction (east-west), the array is connected in a torus. In the Y direction (north-south), the array is connected in a column.

Abstract: The system provides an automated, centralized back-end payroll service with a full-featured web-based payroll system. Both aspects of the system have access to a central database, which includes, for example: profile information on employers and employees; timesheet, salary and hourly wage data; overtime data; employee benefit data; and information regarding third-party providers and miscellaneous payees. The full-featured payroll system functionality is implemented in a manner that provides employers and employees (to the extent security policies permit) with a robust, data-driven user interface via a standard web browser. The central database provides the system's back-end (server-side) payroll service functionality with constant access to the data.

Abstract: A process of fabricating a shallow trench isolation structure includes the steps of: providing a substrate; forming a first insulating layer over the substrate; forming a nitride masking layer over the first insulating layer; patterning and etching the nitride masking layer, the first insulating layer and the substrate to remove portions of the nitride masking layer, the first insulating layer and the substrate thereby forming an exposed trench in the substrate, the trench substantially defining boundaries of the isolation structure; depositing a second insulating layer into the trench and over the nitride masking layer; planarizing the second insulating layer to expose the nitride masking layer; removing the nitride masking layer to expose the first insulating layer, and forming a divot proximate an edge of the trench; depositing a silicon layer into the divot, and over the first insulating later and the second insulating layer; etching the silicon layer to expose the first insulating layer, a central portio

Abstract: The coverification system includes a reconfigurable computing system (hereinafter “RCC computing system”) and a reconfigurable computing hardware array (hereinafter “RCC hardware array”). In some embodiments, the target system and the external I/O devices are not necessary since they can be modeled in software. In other embodiments, the target system and the external I/O devices are actually coupled to the coverification system to obtain speed and use actual data, rather than simulated test bench data. The RCC computing system contains a CPU and memory for processing data for modeling the entire user design in software. The RCC computing system also contains clock logic (for clock edge detection and software clock generation), test bench processes for testing the user design, and device models for any I/O device that the user decides to model in software instead of using an actual physical I/O device.

Abstract: A system and corresponding method for generating multiple phases within a single clock cycle of an input signal is disclosed. The method includes the steps of generating a plurality of output signals from an input source signal, where each of the plurality of output signals represents a phase-shifted version of the input signal. Next, select a pair of signals from the plurality of output signals to act as clock signals, where the selected pair of clock signals define the operating region within which the multiple phases are bounded. Then, provide a pair of complementary weighted bias currents in response to a control signal, where each of the complementary bias currents is used to generate the multiple phases of the present invention. Thereafter, the pair of weighted bias currents presented to a node are adjusted in response to the selected pair of clock signals, where the selected pair of clock signals operates to adjust the rate of change of the weighted bias currents.

Abstract: This present discloses a method for making a concave bottom oxide within a trench, the steps comprising: providing a semiconductor substrate; forming an insulating layer on the semiconductor substrate; defining the insulating layer to form an opening exposing the surface of the semiconductor substrate; dry-etching the exposed semiconductor substrate within the opening by using the first insulating layer as an etching mask to form a trench; depositing a first oxide layer conformably over the insulating layer, the side-walls and the bottom of the trench; depositing a second oxide layer on the first oxide layer and filling-up the trench surrounded by the first oxide layer; annealing to densify the first and second oxide layers; etching-back the first and second oxide layer to remove the portion overlying the first insulating layer, and forming a spacer consisting of the residual first oxide layer on the side-walls of the trench, and a concave bottom oxide consisting of the first and second oxide layers on the bo

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Abstract: A method of forming an isolation structure includes the steps of: providing a silicon substrate; forming an upper pad oxide layer superjacent a top surface of the substrate, and a lower pad oxide layer subjacent a bottom surface of the substrate; forming a nitride masking layer superjacent the upper pad oxide layer, and a lower pad silicon nitride layer subjacent the lower pad oxide layer; patterning and etching the nitride masking layer to expose a portion of the upper pad oxide layer; applying a first etching solution to the exposed portion of the upper pad oxide layer to expose a portion of the substrate substantially defining the boundaries of an active area, and simultaneously forming an undercut cavity by removing a portion of the upper pad oxide layer under the exposed edges of the nitride masking layer surrounding the exposed portion of the substrate; performing an oxidation process to form an etching stop layer over the exposed portion of the substrate and in the undercut cavity, the oxidation proces

Abstract: The present invention provides a system and method that enables users, such as institutional investors and financial institutions, to engage in capital market transactions, including the trading of Over-the-Counter financial products, via the Internet (including the World Wide Web). The system includes a variety of servers, applications, and interfaces that enable users to interactively communicate and trade financial instruments among one another, and to manage their portfolios. Interactive communications supported by the system include: requesting price quotes, monitoring and reviewing quote requests, issuing price quotes, monitoring and reviewing price quotes, negotiation between users, acceptance of price quotes, reporting, portfolio management, analysis of financial information and market data, calendaring, and communications among users and/or system administrators, including e-mail, chat, and message boards.

Abstract: A method and apparatus for processing user-submitted search information to permit a database to be searched regardless of the format and language of the user-submitted information. The user-submitted information is first categorized into one or more categories, where each category is a type of information such as a date, a proper name or a place. For each category pertaining to the user-submitted information, the search is refined by comparing the user-submitted information to a feature table containing specific data types corresponding to each category. From the results of any affirmative comparison with the feature table, a starting location within a corresponding search table is retrieved. The search is further refined by comparing the user-submitted information to the entries of the search table beginning at the starting location. From the results of any affirmative comparison with the search table entries a database address is obtained which is used to obtain a database entry sought after by the user.

Abstract: A method of planarizing a layer of dielectric material is disclosed herein that is particularly suitable for planarizing inter-layer-dielectrics (ILD) or inter-metal-dielectrics (IMD). The planarizing method comprises the steps of depositing a layer of sacrificial oxide over the dielectric material, depositing a layer of amorphous silicon over the sacrificial oxide layer by either sputtering or plasma enhanced chemical vapor deposition (PECVD) at a temperature less than about 500 degrees Celsius, performing a first chemical-mechanical polishing of the amorphous silicon layer to form a self-aligned mask for a subsequent etching step, etching a portion of the sacrificial oxide layer to form a channel therein, and performing a second chemical-mechanical polishing to remove the remaining amorphous silicon layer and the remaining sacrificial oxide, and to substantially planarize the underlying dielectric material.

Abstract: The present invention provides a method for fabricating a field oxide on a semiconductor substrate. A first pad layer and a first mask layer is formed successively on the semiconductor substrate. An opening is formed in the first mask layer to define a region for forming the field oxide. A first field oxide is formed in the opening, which is then removed to form a concave portion. The first pad layer exposed by the concave portion is removed to form a cavity. A second pad layer having a smaller thickness than the first pad layer is formed on the semiconductor substrate. A mask portion is formed in the sidewall of the patterned first mask layer and the cavity. The mask portion in the sidewall of the patterned first mask layer has a thickness less than 300 Å. Finally, thermal oxidation is carried out to form a second field oxide in the concave portion.

Abstract: A method and apparatus for organizing and processing pieces of interrelated information (or “thoughts”) using a digital computer is disclosed. The invention employs a graphical user interface to facilitate user interaction with highly flexible, associative “matrices” that enable users conveniently to organize digitally-stored thoughts and their network of interrelationships. Each of the thoughts may be affiliated with one or more application programs, such as a word processing or spreadsheet utility, or an Internet browser. Users are able conveniently to select a current thought along with any applications or content associated with that thought by interacting with the graphical representation. That representation is automatically reoriented about the selected thought, and is revised to reflect only those thoughts having predetermined relations to that current thought. Users can easily modify the matrix by interactively redefining relations between thoughts.

Abstract: A method of removing a polysilicon buffer in a method of forming a field oxide and an active area is disclosed herein that comprises the step of applying an etching selectivity solution to the polysilicon buffer to substantially remove the polysilicon buffer without substantially affecting the field oxide, a pad oxide, and the substrate. An etching selectivity solution is defined herein is a solution that has an etching rate for one material that is higher than for another material. In this case, the etching selectivity solution has an etching rate for polysilicon material that is higher than its etching rate for field oxide material. Accordingly, when the etching selectivity solution is applied to the polysilicon buffer, it will substantially etch off the polysilicon buffer without substantially affecting the field oxide. In the preferred embodiment, the etching selectivity solution comprises a mixture of HF and HNO3, or HF, HNO3 and CH3COOH.

Abstract: A method of forming a field oxide isolation region includes: forming a first pad oxide layer over a semiconductor substrate; forming a silicon nitride layer over the first pad oxide layer; patterning and etching the silicon nitride layer and the first pad oxide layer to expose a portion of the substrate, and simultaneously forming an undercut cavity; forming a second pad oxide layer over the exposed portion of the substrate; depositing a layer of polysilicon over the second pad oxide layer, the polysilicon layer filling the undercut cavity to form a polysilicon plug; removing portions of the polysilicon layer to form a polysilicon spacer; thermally oxidizing the substrate to substantially consume the polysilicon spacer but leave a polysilicon residual of the polysilicon plug, the thermal oxidation forming a thick oxide above the exposed portion of the substrate; substantially removing the silicon nitride layer; applying a first etching solution to the first pad oxide layer and the polysilicon residual, the fi

Abstract: A multi-user computer system using a communications protocol in transmitting data between a plurality of user interface units is described. The system includes a base unit, which has a bus, a processor coupled to the bus, a display device coupled to the bus, an input device also coupled to the bus, and an interface controller coupled to the bus, wherein said processor controls the operation of the base unit and processes data entered into the base unit and operates to generate output data to be displayed on the display device. The system also includes an auxiliary unit, which has a protocol interface controller, a second display device coupled to the protocol interface controller, a second input device coupled to the protocol interface controller, wherein the protocol interface controller controls the operation of the auxiliary unit and interface with the base unit in accordance with a predetermined communications protocol.

Abstract: An improved process of fabricating a shallow trench isolation structure is provided. A semiconductor substrate is provided and an insulating layer is formed over the substrate. A nitride masking layer is formed over the insulating layer. The nitride masking layer and the insulating layer are patterned and etched to expose a portion of the substrate, and to expose edges of the nitride masking layer and the insulating layer. The exposed portion of the substrate substantially defines boundaries of the isolation structure. A first oxide layer is deposited superjacent the exposed portion of the substrate, and over the nitride masking layer. A removing step includes removing portions of the first oxide layer lying over the nitride masking layer, a central portion of the first oxide layer superjacent the substrate, and a portion of the substrate to form a trench, leaving an oxide spacer disposed between the exposed edges of the nitride masking layer and the insulating layer, and the edge of the trench.