Abstract: A spread-spectrum power converter uses an inter-cycle duty-cycle error compensation to achieve a combination of high-precision tracking of a target average duty cycle and a favorable noise signature. The pulse train consists of a series of cycles having cycle durations of a positive integer of clock cycles, pulse durations of a whole number of clock cycles, and duty cycles corresponding to a ratio of pulse durations over cycle durations. The pulse durations are selected at least in part as functions of a target average duty cycle, the respective cycle durations, and a ripple (or other) error from other cycles in the train. The cycle durations can also be in part a function of the target average duty cycle so that the duty cycle errors can be minimized.

Abstract: A compact vacuum chamber gives electric and optical access to a microchip, which is part of the chamber. The main use of the microchip is to confine, cool and manipulate cold atoms (atom chip). The main new feature is that the microchip forms one wall of a vacuum cell. This makes the chamber compact and lightweight, provides large optical access combined with small overall size, eliminates in-vacuum cabling, and makes the back surface of the chip accessible from the outside (e.g., for cooling and/or additional field-producing elements).

Abstract: A musical instrument controller provides an array keyboard in which most note triggers form major 3rd, minor 3rd, and perfect fifth intervals at line segment boundaries with adjacent note triggers, and form major and minor triads at vertices or other convergence points where three note triggers meet. The segments and vertices provide for single-finger triggering of intervals and triads. After-pressure and movement in the array plane (even crossing trigger boundaries) provide for three dimensions of per-key continuous control.

Abstract: A manual sample injector includes a syringe holder, a plunger driver, and an interface. An interface-control lever attached to the interface can assume “extraction”, “injection”, and “safety” orientations. In its safety orientation, the interface-control lever maintains a syringe needle in a retracted position for safety. Mounting the sample injector on a sample vial forces the interface-control lever to its extraction orientation, which allows the syringe needle to extend into the sample vial for sample extraction. The extent of the needle into the sample vial can be adjusted for precise extraction of sample from non-uniform vial contents. Mounting the injector on an injection port forces the interface-control lever to its injection orientation so that the syringe needle can be extended to an appropriate depth for sample injection.

Abstract: Non-power-of-two Gray-code counters, including modulos 10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register for storing an N-bit, e.g., 4-bit, Gray-code count. The count is converted to binary code by a Gray-to-binary-code counter. The resulting binary count is incremented by an N-bit incrementer that skips certain binary values by toggling least-significant bits in unison when indicated by certain most-significant binary bits. The result is converted to Gray-code by a binary-to-Gray-code translator. The translated result is stored in the register as the next count. An algorithm is disclosed for designing such a Gray-code counter for any even modulo. The modulo is expressed as a sum of positive and negative terms, each term being a power of two. The exponents of the terms determine the counter design.

Abstract: A manual sample injector for a gas chromatograph comprises a syringe holder, a plunger driver including a volume-adjust assembly, an injection port interface, a release lever, and a force-calibration spring. The holder, driver, and interface collectively include guide rod and respective apertures so that the driver and interface can slide vertically relative to the holder. Pre-injection steps provide that the desired volume of sample is ready for injection. Injection steps include: mounting the injector on an injection port by sliding the port interface over a septum cap of the injection port, manually pushing the plunger driver, and thus the syringe holder, down against the resistance of the force-calibration spring until an actuator element of the port interface contacts the cocked release lever, increasing the downward force on the plunger driver so that the release lever is forced to a release position.

Abstract: An external power-management device controls the supply of electric power from a wall outlet to a refrigerated vending machine. The system includes a switch that couples power in an ON condition and decouples in an OFF condition. The switch is controlled by a controller based on data received from a current sensor, an occupancy sensor, a temperature sensor, and a time-of-year circuit. Upon startup, the current is monitored to determine maxima and minima for the vending machine. The system supplies power to the appliance during business hours as indicated by the time-of-year circuit and while the vicinity is occupied as determined by the occupancy sensor irrespective of the values for current and temperature. Absent the current sensor, the power would be decoupled after a predetermined duration of non-occupancy during nonbusiness hours.

Abstract: Copper is the bulk interconnect metal in the manufacture of an integrated circuit in accordance with the damascene process. When copper is exposed through via apertures, carbon monoxide and hydrogen are used as reduction agents to convert black copper oxide to red copper oxide and the red copper oxide to copper. The integrated circuit is then transferred in a high vacuum to a sputter chamber so that re-oxidation does not occur before tantalum barrier metal can be deposited. As a result, a good tantalum-copper electrical contact can be made without risking embedding copper in oxide sidewalls (whence it could migrate to active circuit regions and impair device reliability).

Abstract: An integrated circuit includes a substrate with doped regions, a patterned polysilicon layer defining contacts and local interconnects, a submetal dielectric, a two-metal layer metal interconnect structure with an intermetal dielectric layer, and a passivation layer. Like the dielectric layers, the passivation layer is optically transparent, thick, and planarized. Because of this, laser energy can be directed through the passivation layer to fuse two conductors of the top metal layer without delaminating the passivation layer. In addition, laser energy is directed through the passivation layer and the intermetal dielectric to fuse pairs of conductors in the lower metal layer. Thus, the present invention provides for reliable convenient circuit modification without disturbing dielectric and exposing metal features to moisture and other contaminants.

Abstract: A thyristor-based forward phase control (FPC) system for controlling the power delivered to a load from an AC power source employs a short-circuit test cycle to protect the thyristor from damage. Upon activation of the FPC system, the thyristor is triggered at a phase less than one-twelfth cycle before a zero crossing so that, if there is a short, the resulting peak current will be insufficient to damage the thyristor but will exceed a predetermined threshold current corresponding to a repetitive overload current. If during the test cycle, the threshold current value is crossed, the FPC system does not trigger the thyristor again and does indicate that a short exists. The threshold current value is selected to correspond to the thyristor's steady-state load rating. If it is exceeded during normal (including warm-up and request-based) operation, steps can be taken to address an overload condition.

Abstract: An-on-chip decoupling capacitor system for an integrated circuit comprises parallel capacitive and fusible paths between power and ground. The capacitive path includes a field-effect-transistor based capacitor and another "capacitive-path" transistor in series with the capacitor. The fusible path includes an electromigratable fuse and a "fusible-path" transistor in series with the fuse. The capacitive-path transistor, which is controlled by the voltage at a "fusible-path" node between the fuse and the fusible-path transistor, is on during normal operation. The fusible-path transistor, which is controlled by the voltage at a "capacitive-path" node between the capacitor and the capacitive-path transistor, is off during normal operation. During normal operation, the capacitor provides local voltage regulation by sinking charge during voltage surges and supply charge during voltage drops.

Abstract: An integrated circuit manufacturing method uses chemical-mechanical polishing (CMP) to planarize a nonplanar submetal (or intermetal) silica dielectric layer. The planarized device is cleaned with an aqueous solution of ammonium hydroxide and citric acid. Exposed hydrated silica is etched using mixture of nitric and hydrofluoric acids, freeing embedded contaminants from the CMP slurry. The hydrofluroic acid is the etching agent, while the nitric acid combines with the freed contaminants to render water soluble products. They are thus carried away in an aqueous rinse, whereas otherwise they might recontaminate the device. A metal interconnect structure is formed on the etched oxide by forming contact apertures, depositing metal, and patterning the metal. The method can be applied also to nonplanar intermetal dielectrics and subsequent metal interconnect layers. The result is an integrated manufacturing method with higher yields and a more reliable manufactured integrated circuit.

Abstract: A floating-point processor nominally capable of single and double, but not extended, precision execution stores operands in extended-precision format. A format converter converts single and double precision source values to extended-precision format. Trap logic checks the apparent precision of the extended-precision operands and the requested result precision to determine whether the floating-point processor can execute the requested operation and yield the appropriate result. If the maximum of the requested precision and the maximum apparent precision of the operands is single or double, the requested operation is executed in hardware. Otherwise, a trap is issued to call an extended precision floating-point subroutine. This approach augments the class of operations that can be handled in hardware by a double-precision floating-point processor, and thus improves the floating-point computational throughput of an incorporating computer system.

Abstract: In the manufacture of an integrated circuit, contaminated oxide is replaced by relatively pure oxide using the following steps. First, a partially manufactured integrated circuit is bathed in an aqueous solution of hydrogen peroxide and ammonium hydroxide to oxidize organic materials and weaken bonds of metal contaminants to the integrated circuit substrate. Second, an aqueous rinse removes the oxidized organic materials and metal contaminants. Third, the integrated circuit is bathed in an aqueous solution of hydrogen fluoride and nitric acid. The hydrogen fluroide etches the contaminated oxide; the nitric acid combines with calcium and metal contaminants freed as the oxide is etched. The resulting nitride byproducts are highly soluble and easily removed in the following aqueous rinse. A drying step removes rinse water from the integrated circuit. Finally, an oxide formation step provides a relatively pure oxide layer.

Abstract: A microprocessor includes a programmable instruction trap that can be used to deimplement instructions that lead to erroneous results. Upon discovery of a logic design defect, a microprocessor manufacturer can distribute an updated exception handler and a patch for a boot sequence. Upon power up, the boot sequence programs instructions to be deimplemented into a trap list. Each received instruction (issued by an application program, for example) not matching any listed instruction is executed in due course. When it matches a listed deimplemented instruction, the received instruction is trapped: it is not executed but is stored in a dedicated register. An exception handler is called that can examine the trapped instruction and substitute a suitable routine. If the trapped instruction is conditionally deimplemented and the problematic conditions do not pertain, the exception handler can reissue the instruction after temporarily deactivating the trapping function.

Abstract: A counting system with a dynamic maximum count includes a counter, match logic, and a maximum count controller. The counter has a present count register, a clock (or event indicator) event input, and a reset input. The maximum count controller can be programmed with an adjustable maximum count stored in a maximum count register. The match logic includes a count-wide AND gate fed by NAND gates. Each NAND gate has an inverted input coupled to a respective bit position of the present count register and an uninverted input coupled to a respective bit position of the maximum count register. The function of the match logic is to indicate a match whenever the present count has a 1 at every bit position that the maximum count has a 1, irrespective of the present count values at bit positions at which the maximum count has 0s. Thus, imperfect matches are provided for. The values of the imperfect matches always exceed the values of perfect matches, so they are not usually encountered.

Abstract: A sputter deposition system includes a mobile collimator. The collimator can be magnetically moved into and out of a position between a wafer and a target of material to be sputtered onto the wafer. In addition, magnets are used to levitate the collimator so that it can be removed without solid-solid friction, and the contamination it can cause. The magnets used for levitation are part of a control loop that maintains the orientation of the collimator parallel to the wafer. The system allows for a combination of good deposition step coverage and high fabrication throughput while minimizing opportunities for contamination and breakage that can occur when the wafer is transferred between chambers.

Abstract: A computer system includes a microprocessor running in big-endian mode and both big-endian and little-endian peripherals, including a little-endian SCSI controller that controls a hard disk. When a program calls for a data transfer between the hard disk and random-access memory, the operating system determines a peripheral-accessible memory address range for the data transfer. A bridge driver intercepts this range and determines whether or not the data needs to be swizzled to take into account differing endianness. The determination is encoded into the most significant bit of a processor-assertable address range, and the bits of lesser significance indicate the peripheral-accessible address range. The processor-assertable address range is conveyed to the SCSI controller originating the data transfer. A communications bridge extracts the processor-assertable address from the origination information from the SCSI controller.

Abstract: An integrated circuit includes a substrate with doped regions, a patterned polysilicon layer defining contacts and local interconnects, a submetal dielectric, a two-metal layer metal interconnect structure with an intermetal dielectric layer, and a passivation layer. Like the dielectric layers, the passivation layer is optically transparent, thick, and planarized. Because of this, laser energy can be directed through the passivation layer to fuse two conductors of the top metal layer without delaminating the passivation layer. In addition, laser energy is directed through the passivation layer and the intermetal dielectric to fuse pairs of conductors in the lower metal layer. Thus, the present invention provides for reliable convenient circuit modification without disturbing dielectric and exposing metal features to moisture and other contaminants.

Abstract: A data processing system includes a microprocessor, memory, and an instruction substitution filter. The microprocessor has separate data and instruction caches. The filter includes configuration memory that occupies memory mapped I/O space. Configuration data indicating instruction types to be deimplemented is entered into the filter during a boot sequence. Once configured, the filter substitutes call instructions for the deimplemented instructions. When executed, the call instructions activate a substitution routine that determines the address of the deimplemented instruction and then performs a data read of the unfiltered deimplemented instructions and then implements the function that the deimplemented function was intended to implement (but, due to microprocessor defects, does not). Accordingly, the present invention allows a microprocessor with defectively implemented instructions to be used as intended with minimal performance penalties.