Abstract: A digital signal regenerator comprises a quantizer, a sampler, a timing extractor and a frequency and phase locked loop. The included frequency locked loop employs a frequency difference detector and a frequency generator which it shares with the included phase locked loop. The frequency difference detector includes flip-flops for generating square wave frequency difference signals, obviating the need for the multipliers, comprators and low pass filters used in prior devices. In addition, the frequency difference detector includes pulse-width modulator which is controlled by a pulse-width regulator. The regulator provides for a constant loop gain for the frequency locked loop over different reference frequencies output by the frequency generator.

Abstract: Oxygen determination based on luminescence quenching of fluorescent dye is effected by using the frequency output of an offset-phase locked loop to calculate the time constant for the exponential decay of fluorescence. An offset phase angle between a periodic stimulus signal used to excite the dye and a response signal based on fluorescence detection is predetermined to optimize signal-to-noise ratio for a wide range of time constants. An offset-phase locked loop is used to vary the frequency of a periodic stimulus signal until the predetermined phase relationship is established. Where the stimulus and response signals are substantially sinusoidal, the offset phase angle is ideally about 49.3.degree., although substantially optimal performance is achieved using a more conveniently generated 45.degree.. The 45.degree. angle offset can also be used with a square-wave stimulus signal.

Abstract: An emitter-coupled multiplexer has all transistors directly controlled by one select signal in parallel with transistors directly controlled by other select signals. Thus, in a 3:1 multiplexer (100), a first select signal (S0) directly controls one transistor (Q13); this transistor is in parallel with another transistor (Q14) which is directly controlled by a second select signal (S1). The second select signal also directly controls another transistor (Q15) in the same network (102). This transistor is in parallel with a transistor directly controlled by an input signal (I1) which is thus masked when the second select signal is activated. The second select signal also controls (at Q16 and Q18) subnetwork selection in another current network (104) of the multiplexer. The disclosed arrangement permits the multiplexer function to be implemented with a reduced transistor count and only two current sources in two-level series gating.

Abstract: A multiplexer with inhibit is implemented so that an active inhibit signal effectively sets the select signals to block all but the selected input signal and effectively masks the selected input signal. In the case of the disclosed emitter-coupled logic 4:1 multiplexer, enable signal controlled transistors (Q24 and Q25) are in parallel with transistors (Q14 and Q15) respectively controlled by the select signals (S0 and S1). Activating the enable signal (EN) effectively selects one input (A3) and blocks the others (A0, A1 and A2). A third enable activated transistor (Q35) is in parallel with the transistor (Q13) controlled by the selected input (A3). The activated enable masks the selected signal to complete the inhibit function. Thus, a standard function is implemented with a reduced free-standing and total transistor count.

Abstract: A two-level series gating complementary output master-slave D-type flip-flop (100) with multiplexed input incorporates a novel current-splitting network (108). The flip-flop includes a master latch (102), a slave latch (104) and a 2:1 multiplexer (106) incorporated into the master latch. The multiplexer includes a pair of matched, emitter-coupled, collector-uncoupled transistors (Q12 and Q13), the bases of which are tied to a reference voltage (VBB2). When a clock pulse (CP) is low, substantial network current flows through both matched transistors. This arrangement allows the circuit function to be implemented with a reduced transistor count and only two current sources. The master latch output (QM) is determined by the voltage at the base of an output transistor (Q21), which voltage is determined by the presence or absence of a current through a load resistor (RL1).

Abstract: A microprocessor integrated circuit (50) has a read only memory (ROM) (400) which is X and Y addressible and is word, bit and page oriented. The microprocessor integrated circuit (50) has a main injector bus (602) and a ground return bus (604) with a branch ground bus (608) connected to the ground return bus (604) through a ground-balancing resistor (610) in a data path. The circuit (50) has a register file (82) with registers (622) connected to a local bus (604). The local busses (604) are connected to a main bus (602) through a multiplexer (605). The microprocessor integrated circuit (50) includes a D-type flip-flop circuit (700) with asynchronous clear and preset. A latch dual port random access memory (RAM) circuit (900) is employed in the register file (82) of the microprocessor integrated circuit (50).

Abstract: A microprocessor data processing system (1700) includes system units (50, 1704) connected to a bus (1702), with a bus arbiter (1712) and a protocol for assigning bus access to the system units (50, 1704). The microprocessor (50) executes both arithmetic operations and floating point operations. A microcontrol store (162) stores common instructions usable in different floating point operations. A PLA (180) supplies addresses to microcontrol store (162) and provides a signal indicating floating point instruction type. The microprocessor (50) includes a pending interrupt register (250) connected to mask and enable logic (268). The mask and enable logic (268) is connected to a priority encoder (278), which is connected to an interrupt latch (282). The latch (282) supplies outputs to generate a current state storage address.

Abstract: A digital and linear dynamic ignition control apparatus comprising a burn-time counter, a pre-dwell counter, a current limit counter, engine speed detection apparatus, a biasing circuit and an excess current limit circuit is provided for controlling the start of a dwell in each ignition period. In operation, a current limit adjust window is established for each period. The time of the termination of a dwell in the period relative to the current limit adjust window established for the period starts the dwell in the next period relative to the beginning of the next period at a time calculated to optimize engine performance and minimize energy losses. In general, rapid acceleration in a period starts the dwell earlier in the next period to insure adequate charging of the ignition coil. Conversely, rapid deceleration in a period starts the dwell later in the next period to minimize energy losses.