Abstract: The present invention is directed to semiconductor chip analysis involving evaluation of a thickness of material in the chip, for example, as the chip is being thinned. According to an example embodiment of the present invention, a semiconductor die having a buried insulator (BIN) layer between a circuit side that is opposite a back side is analyzed. Light is directed at a selected area at the back side that is over a portion of material that has been reduced in thickness relative to the thickness of an unaltered die. The light has sufficient intensity to pass through the BIN layer and sufficient photon energy to cause the generation of electron-hole pairs in the die on the side of the BIN layer opposite the back side of the die. The electron-hole pairs generate an electrical output from the semiconductor die that is monitored and used to evaluate the thickness of the material.

Abstract: Semiconductor structures having dielectric material layers that are below 3 nanometers in thickness can now be measured with greater precision and in less time using a SIMS device. In an example embodiment of the present invention, a method of measuring the thickness of a dielectric material layer of a semiconductor structure formed on a substrate includes directing a high energy ion beam at a portion of the substrate and sputtering off a plurality of targeted ions from the substrate. The thickness of the dielectric material layer is then determined as a function of a dosage level of the targeted ion and a density of the targeted ion in the dielectric material.

Abstract: Post-manufacturing analysis of a semiconductor device is enhanced via a method that uses a light emitting diode (LED) formed in a semiconductor die. According to an example embodiment of the present invention, a LED is formed within a semiconductor die having a circuit side opposite a back side. The LED is activated and generates radiation. Substrate is removed from the device, and the amount of radiation that passes through the substrate is detected. The amount of radiation that passes through the die is a function of the absorption characteristics of the die and the substrate thickness. By detecting the radiation and using the absorption characteristics of the die, the amount of substrate remaining in the back side of the die is determined and the substrate removal process is controlled therefrom.

Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.

Abstract: A system and method for controlling the manufacture of semiconductor wafers using model predictive control is provided. In accordance with one embodiment, a tool output of the manufacturing tool is determined based on a first wafer run. Using the tool output, a tool input for a subsequent wafer run is determined by minimizing an optimization equation being dependent upon a model which relates tool output to tool process state and tool process state to tool input and previous tool process state. The tool input is then provided to the manufacturing tool for processing a second wafer run. In this manner, processing by the tool or tool age is taken into account in determining the tool input for a subsequent run. This can reduce variations in tool output from run-to-run and improve the characteristics of the ultimately formed semiconductor devices.

Abstract: A microprocessor circuit arrangement is capable of retrieving and executing program instructions from a program memory having one of multiple possible bit-widths using address signals. A microprocessor uses a set of program instructions to select a memory configuration for retrieving the program instructions. The program memory stores the set of program instructions such that the microprocessor can retrieve the set of program instructions regardless of which bit-width is used to store the set of program instructions. Additional circuitry maps the address signals for retrieving the program instructions from the program memory.

Abstract: The encoder arrangement and bit-exact IDCT protocol provides methods and arrangements that prevent an accumulation of errors between a transmitting codec and a receiving codec. One example embodiment is directed to an arrangement for use in a first terminal for communicating representations of images with a second terminal using a communications channel on which communication has been established between the first terminal and the second terminal. The arrangement includes a processor-based decoder/encoder circuit and a bit-exact circuit. The processor-based decoder/encoder circuit is arranged to process video data using an inverse transformer loop. The bit-exact circuit prevents unacceptable accumulation of an error within the inverse transformer loop by using the inverse transformer in the loop according to a bit-exact specification between the encoder and decoder in the respective first and second terminals.

Abstract: A semiconductor structure with a heavily doped buried breakdown region and a method for manufacture. A source region is disposed in a substrate and is doped with dopant of a type opposite that of the substrate. A drain region is disposed in the substrate at the surface and doped with dopant which is the same as that of the source region, and a gate structure is disposed on the substrate between the source and drain regions. A breakdown region is disposed in the substrate below the drain region and is heavily doped with dopant of a type opposite that of the drain region in order to control the value and location of breakdown.

Abstract: The stress dislocations formed in a substrate by semiconductor processing are significantly reduced, if not eliminated, by subjecting the substrate to a high temperature post sacrificial oxide anneal that causes viscous flow of the oxide over the substrate. In one example embodiment, a method of forming a semiconductor structure includes forming a first oxide layer over a substrate and forming a first dielectric material layer over the first oxide layer. An opening is then etched in the oxide and dielectric layers thereby exposing the substrate. A trench is formed with a desired depth in the substrate in the opening provided, followed by a deposition of an insulator material in the trench. The first dielectric layer and a portion of the insulator material is then removed leaving a portion of the insulator material within the trench. Applications include logic circuits having embedded-DRAM and circuits directed to stand-alone logic or stand-alone DRAM.

Abstract: A videophone apparatus with an on-screen telephone keypad user-interface. The videophone communicates video and audio data over a plain old telephone service (POTS) line and includes a video source and a communication channel interface circuit coupled to a programmable processor. The programmable processor is configured and arranged to execute a user interface program for user controlled operation of the videophone apparatus, display a first menu on the display, the first menu referencing a first plurality of options for operating the videophone apparatus and having associated therewith respective indicators of telephone keypad buttons, receive from the telephone keypad a first selection signal indicative of a pressed button, and initiate an operation to control the videophone apparatus in response to the first selection signal.

Abstract: According to one aspect of the disclosure, the present invention provides methods and arrangements for the removal or reduction of divergence artifacts between a transmitting codec and a receiving codec.

Abstract: A variable length coding system encodes and decodes symbols as uniquely decodable code words using an assignment scheme having a maximum code word length. According to one embodiment, a first bitstream is combined with a second bitstream to provide a resultant bitstream to be sent over a communications channel. The first bitstream represents the code words in a forward direction, and the second bitstream contains the same code words reversed and bit delayed by at least the maximum code word length. A resultant bitstream can be decoded in forward or reverse direction. The scheme is highly efficient for long blocks of data and the reversible aspect of the coding scheme improves the tolerance for errors caused by channel interference.

Abstract: A fabrication process benefits high-density DRAM cells, including four-Gbit cells and beyond. In one embodiment, a poly-Si pillar transistor is formed on top of a trench capacitor with the top of the pillar transistor being directly connected to the bit line. To reduce the process steps, word line formation is achieved by a spacer etch process and a self-aligned process is used for formation of bit line contact using a CMP process. This embodiment reduces necessary layout area and provides improvements in overall device performance.

Abstract: The present invention is directed to an apparatus for use in internal surgical procedures and is particularly advantageous for use in laparoscopic surgical procedures. An example implementation is directed to a tool having a depth-adjustable cannula having an upper portion that rests on the body, and having an automatically-sealing channel that readily accepts the insertion and removal of surgical instruments without permitting gases to pass. In one particular embodiment, the tool includes a low-profile platform for stabilizing the tool on a body layer, a projection channel with a flexible sleeve for maintaining the channel closed, and an adjustable member for setting the penetration depth of the tool. The flexible sleeve is sufficiently elastic to close the inner channel in response to pressurization between the outside of the flexible sleeve and the inner surface of the hollow channel. The low-profile platform and the adjustable member permit use of the same tool for different body-wall thicknesses.

Abstract: According to one aspect of the disclosure, the present invention provides methods and arrangements for the removal or reduction of divergence artifacts between a transmitting codec and a receiving codec. One of a number of implementations includes using a deblocking filter in an inverse transformer loop and selectively disabling the filter upon certain conditions.

Abstract: An apparatus and method for the determination of a depth profile and/or one or more depth profile characteristics of a dopant material in a semiconductor device includes a light source which can illuminate the device at two or more illumination wavelengths, a detector that receives scattered light from the semiconductor device and determines an intensity characteristic for one or more Raman spectral lines attributable to the presence of the dopant material in the semiconductor device. The intensity characteristics of the Raman spectral lines can then be used to determine the depth profile or depth profile characteristics using profile constants measured from known samples at each of the illumination wavelengths. This apparatus and method can be used in-line because it is noninvasive, relatively quick, and nondestructive.

Abstract: A system for performing high speed exponentiation in a secure environment. The system includes an interface for receiving encrypted data sent from a host system, a plurality of exponentiators capable of operating concurrently, an encyptor decrypting data received from a host system and encrypting data produced from the exponentiators, and logic circuitry for selecting an available and properly functioning exponentiator to perform exponentiation on the received data.

Abstract: A method for partial parallel testing a plurality of integrated circuit packages using a multi-package tester head having a plurality of sockets. Each socket is used for testing an integrated circuit package. A first one of the sockets has a full complement of signal channels, and the other sockets have exclusive subsets of the full complement of signal channels. The first socket and the other sockets support parallel testing of the integrated circuit packages according to a first type of test. Only the first socket, with its full complement of signal channels, supports a second type of test. To test a plurality of integrated circuit packages, a group of packages are inserted in the sockets. A first-pass test is then performed, in parallel, on the packages in the sockets. Then, for packages that passed the first-pass test, second-pass testing is performed sequentially using the first socket.

Abstract: A micro-computer is arranged to execute instructions for data intensive applications, such as those used in mobile communications. One particular embodiment involves processing instructions into computational codes and data management codes. These two parts are coded separately and issued to two different program decoders in parallel. Computational codes control the computational units with register-to-register data movement only. Data management codes control data movement through the data management unit to prepare and transfer data for the computation. Multiple register files with active file swapping scheme may be used to simplify the computational operations without decreasing performance. The arrangement provides a significant reduction in power and is, therefore, especially advantageous for battery-operated communication applications and devices.