Abstract: A semiconductor device may be fabricated using a process in which a group of transistors connected between a high and low voltage sources are formed. The transistor among the group of transistors which is used for connection to the high voltage source has non-symmetrical source and drain regions. The device, exploits low operating voltages to construct new high performance transistors.

Abstract: According to one aspect of the invention, a method of fabricating N+ and P+ silicided gates limits diffusion when using a Tungsten, Titanium or Cobalt silicide in the gate fabrication. An example method involves doping a polysilicon structure in first and second dual gate regions and on either side of an undoped polysilicon region, forming a silicide is over the polysilicon structure, and then stuffing the undoped polysilicon region with a species selected to inhibit lateral diffusion of dopant from the polysilicon in the silicide. Subsequently, each gate is completed so that is includes a dielectric layer arranged over the silicide and one of the doped gate poly regions. Applications include logic circuits having embedded-DRAM, and circuits directed to stand-alone logic or stand-alone DRAM.

Abstract: A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.

Abstract: A system and method for video data processing for searching a region of overlapping candidate blocks to locate the best match to a comparably sized reference block comprising plurality of tree adder computational structures which each calculate the sum of absolute difference values for the corresponding data pixels in the comparison. The system further comprises a memory and addressing configuration comprising a dual part RAM, a funnel shifter, and control logic to supply the necessary data pixel values to allow the plurality of tree adders to compute the sum of absolute difference values for adjacent locations concurrently. Another aspect of the system and method for video processing is accumulating two values representing mathematical comparisons of two multi-dimensional images performed in a pixel-wise manner to determine which of the comparison produces less of a difference between the compared images.

Abstract: A process for forming a semiconductor device using a conductive etch stop. The process includes the steps of fabricating a wafer structure up to a first level oxide deposition. A conductive etch stop is deposited over the first level oxide deposition, and selected portions of the conductive etch stop are removed. An inter-level oxide layer is deposited on the conductive etch stop, and selected portions of the inter-level oxide deposition are etched up to the conductive etch stop. The conductive etch stop may be either removed from the semiconductor or left as a conductor.

Abstract: A process for making a high performance MOSFET with a scaled gate electrode thickness. In one embodiment, the process comprises first providing a substrate. A gate dielectric layer is formed on the substrate, and a gate electrode is formed on the gate dielectric layer. A middle portion of the gate electrode has a first height, and side portions of the gate electrode have heights that are less than the first height. A dopant species is implanted at a first energy level and at a first concentration, whereby lightly doped drain regions are formed in the substrate below the side portions of the gate electrode.

Abstract: A semiconductor device and process for manufacture thereof is disclosed in which a gate electrode with reduced overlap capacitance is formed by forming a gate electrode on a surface of a semiconductor and doping edge portions of the gate electrode with a first doping which effectively reduces the conductivity of the edge portions of the gate electrode. The conductivity of the gate electrode may be reduced at the edge portions by doping the edge portions with a dopant which inhibits the doping of the gate electrode or with a dopant which has a different conductivity type than the gate electrode dopant.

Abstract: A system and method for modeling activities of people in an organization. The organization is modeled using definitions of processes performed by the organization, definitions of data elements generated by the entities performing the processes, and definitions of relationships between the data elements generated and the processes. Each relationship definition symbolizes a data element provided by a first one of the processes and required by a second one of the processes. In an example embodiment, the database is accessible to a server system, and a client system is coupled to the server system. Responsive to an input control signal at the client system, a request is sent to the server system for organization modeling data. The client system displays the organization modeling data, wherein processes are depicted as nodes on a graph and the data elements are depicted as directed edges connecting nodes. The system also models events that cause transitions between the processes.