Abstract: A semiconductor device includes a substrate (12), a first insulating layer (14) over a surface of the substrate (12), a layer of nanocrystals (13) over a surface of the first insulating layer (14), a second insulating layer (15) over the layer of nanocrystals (13). A nitriding ambient is applied to the second insulating layer (15) to form a barrier to further oxidation when a third insulating layer (22) is formed over the substrate (12). The nitridation of the second insulating layer (15) prevents oxidation or shrinkage of the nanocrystals and an increase in the thickness of the first insulating layer 14 without adding complexity to the process flow for manufacturing the semiconductor device (10).

Abstract: First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes referenced to the second power supply domain by a clocked level shifter that couples the first circuitry to the second circuitry and buffers the data signal from the first power supply domain to the second power supply domain by only using a single supply voltage. The clocked level shifter is clocked by a signal that is used to precharge a first node and a second node of the clocked level shifter until the data signal is valid for at least a setup time period. The first and second nodes are precharged to establish a known state in the clocked level shifter.

Abstract: An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block having a power supply voltage terminal for receiving a second power supply voltage and an input terminal coupled to the output terminal of the first circuit block for receiving the first data signal. The integrated circuit further includes a first programmable delay block for adding a first delay time to the first data signal when one or both of the first or second power supply voltages is changed.

Abstract: A method is provided for detecting a stall condition in a stepping motor. The stepping motor has two coils and a rotor, and is micro-stepped by substantially continuously driving both of the two coils with out-of-phase time varying voltages. The method includes stepping the stepping motor to a next micro-step. It is then determined when a predetermined motor parameter of a first coil of the two coils is to be sampled. To sample the predetermined motor parameter of, for example, the first coil, the first coil is opened for a predetermined period, wherein the predetermined period is less than or equal to a micro-step. Then the first coil is sampled during the predetermined period and the result of sampling is integrated and used to increment or decrement an accumulated value. If the accumulated value is less than a preset value, then a stall condition exists.

Abstract: A memory has first and second memory arrays and first and second sense amplifiers coupled to the first and second memory arrays, respectively. A verify data line is coupled to first outputs of the first sense amplifier and the second sense amplifier as well as to a program/erase controller. The verify data line has a first logic circuit having a first input coupled to the first output of the first sense amplifier and an output. A second logic circuit has a first input coupled to the output of the first logic circuit, a second input coupled to the first output of the second sense amplifier, and an output. A global data line is coupled to a second output of the first sense amplifier and a second output of the second sense amplifier. A global sense amplifier is coupled to the global data line.

Abstract: A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, including a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value. The method further includes if a read data error occurs when data is read from a set of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is greater than the first value.

Abstract: An AM receiver including an AM demodulator for demodulating an AM signal received by an antenna coupled to the AM demodulator is provided. The AM receiver further includes a bandpass filter for receiving the demodulated signal and generating a bandpass filtered signal. The AM receiver further includes a moving average filter for receiving the bandpass filtered signal and generating a moving averaged signal and a highpass filter for receiving the moving averaged signal and generating a highpass filtered signal. The AM receiver further includes an averaging filter for receiving the highpass filtered signal and generating an averaged signal and a summer for receiving the averaged signal and the highpass filtered signal and generating a difference signal. The AM receiver further includes a comparator for generating a noise blanking signal based on a comparison of the difference signal with a threshold.

Abstract: A circuit comprises first, second, third, and fourth transistors. The first transistor has a first current electrode, a control electrode for receiving an input signal, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor for providing an output signal, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to a first power supply voltage terminal. The third transistor has a first current electrode coupled to a second power supply voltage terminal, a control electrode, and a second current electrode coupled to the first current electrode of the first transistor. The fourth transistor has a first current electrode coupled to the control electrode of the third transistor, a control electrode coupled to the control electrodes of the first and second transistors, and a second current electrode coupled to the control electrode of the first transistor.

Abstract: In one embodiment, a method of programming an oscillator circuit includes providing a resonator, a first programmable capacitor, a second programmable capacitor, and an amplifier. The first programmable capacitor and the second programmable capacitor may be programmed at a first capacitance value during a first time period, wherein the first programmable capacitor provides a first voltage to bias the resonator and the amplifier alters the second voltage to provide a third voltage to the resonator. During a second time period the first capacitance value is increased.

Abstract: A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with the result that the blocks with different histories erase differently. Thus, after a predetermined number of erase cycles are performed, the ability to parallel erase is prevented. This is achieved by allowing parallel erasing operations until the predetermined number of erase operations have been counted. After that predetermined number has been reached, a parallel erase mode disable signal is generated to prevent further parallel erase cycles. The count and the predetermined number are maintained in a small block of the non-volatile memory that is inaccessible to the user.

Abstract: A switching amplifier includes a power stage, a low pass filter, a combining circuit, and a feedback correction circuit. The power stage has an input terminal and an output terminal. The low pass filter has an input terminal coupled to the output terminal of the power stage, and an output terminal for providing a filtered pulse width modulated signal. The combining circuit has a first input terminal coupled to the output terminal of the power stage, a second input terminal coupled to the output terminal of the low pass filter, and an output terminal. The feedback correction circuit has a first input terminal for receiving a reference pulse width modulated signal, a second input terminal coupled to the output terminal of the combining circuit, and an output terminal coupled to the input terminal of the power stage.

Abstract: A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage. A shorting device selectively electrically short circuits the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device. The shorting device is smaller in size than the power gate device.

Abstract: A micro electromechanical switch has a movable portion positioned to form an electrical connection between a first electrical contact and a second electrical contact. A piezoelectric electrode is formed on the movable portion. The piezoelectric electrode causes the movable portion to move in response to a driver voltage. A piezo element is formed on the movable portion of the switch. The piezo element is for detecting movement of the movable portion between an open position and a closed position. The piezo element is also used to detect switch bouncing when the switch transitions from the open position to the closed position. In one embodiment, the piezo element is a piezoelectric element and in another embodiment the piezo element is a piezo-resistive element.

Abstract: A flip-flop includes a master latch, a first inverter, a slave latch, and a first clocked inverter. The master latch has an input for receiving an input signal and an output. The first inverter has an input coupled to the output of the master latch and an output for providing an output of the flip-flop. The slave latch is directly connected to the input of the first inverter. The first clocked inverter has an input directly connected to the slave latch and an output coupled to the master latch.

Abstract: An amplifier comprises first, second, and third modulators. The first modulator includes an input for receiving a first input signal, and an output for providing a first modulated output signal corresponding to the first input signal. The second modulator includes an input for receiving a second input signal, and an output for providing a second modulated output signal corresponding to the second input signal. The third modulator has an input for receiving a third input signal, and an output for providing a third modulated output signal corresponding to the third input signal and for providing a virtual ground. A first amplifier circuit is coupled to the outputs of the first and third modulators for driving a first load. A second amplifier circuit is coupled to the outputs of the second and third modulators for driving a second load.

Abstract: A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus. An instruction is received which indicates an effective address. The instruction is executed and it is determined if the effective address results in a hit or a miss in the cache. If the effective address results in a hit, data associated with the effective address is provided from the cache to the system bus without modifying a state of the cache. The instruction allows real-time debugging circuits to be able to view the current value of one or more variables in memory that may be hidden from access due to cache hierarchy without modifying the value or impacting the current state of the cache.

Abstract: A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values.

Abstract: An apparatus and method are provided for accessing a serial memory without knowing the required number of address bits. The apparatus comprises a pull circuit, a data out control circuit and a transition detector. The pull circuit causes the input terminal to be set to a first predetermined logic state in response to a read command being provided to the serial memory. The data out control circuit has an output terminal for providing the read command and a first predetermined number of address bits to the output terminal. The transition detector is coupled to an input terminal for detecting if the input terminal transitions from the first predetermined logic state to a second predetermined logic state in response to the first predetermined number of address bits. The transition detector will detect a transition of the input terminal when a correct number of address bits have been provided.

Abstract: An integrated circuit (10) comprises a plurality of non-volatile memory cells (14) and a charge distribution ramp rate control circuit (11). Each memory cell of the array (12) includes a charge storage region and a plurality of terminals. The charge distribution ramp rate control circuit includes a capacitor (62,116,144) having a first plate electrode coupled to at least one terminal of the plurality of terminals, and a second plate electrode. The charge distribution ramp rate control circuit further includes a bandgap generated current source (58,106,136) for providing a reference current to determine a ramp rate of a voltage at the at least one terminal.

Abstract: An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells.