Abstract: A bi-directional transient voltage suppression device with symmetric current-voltage characteristics has a lower semiconductor layer of first conductivity type, an upper semiconductor layer of first conductivity type, and a middle semiconductor layer adjacent to and disposed between the lower and upper layers having a second opposite conductivity type, such that upper and lower p-n junctions are formed. The middle layer has a net doping concentration that is highest at a midpoint between the junctions. Furthermore, the doping profile along a line normal to the lower, middle and upper layers is such that, within the middle layer the doping profile on one side of a centerplane of the middle layer mirrors the doping profile on an opposite side. In addition, an integral of the net doping concentration of the middle layer taken over the distance between the junctions is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.

Abstract: In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided.

Abstract: A trench MOSFET includes a plurality of trench segments in an upper surface of an epitaxial layer, extending through a second conductivity type region into a first conductivity type epitaxial region, each segment at least partially separated from an adjacent segment by a terminating region, and the trench segments defining a plurality of polygonal body regions within the second conductivity type region. A first insulating layer at least partially lines each trench and a plurality of first conductive regions are provided within the trench segments adjacent to the first layer. Each of the conductive regions is connected to an adjacent conductive region by a connecting conductive region, overlying the terminating region, that bridges at least one of the terminating regions, and a plurality of first conductivity source regions are within upper portions of polygonal body regions and adjacent the trench segments, the source regions positioned outside the terminating regions.

Abstract: A trench MOSFET device and process for making the same are described. The trench MOSFET has a substrate of a first conductivity type, an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate, a plurality of trenches within the epitaxial layer, a first insulating layer, such as an oxide layer, lining the trenches, a conductive region, such as a polycrystalline silicon region, within the trenches adjacent to the first insulating layer, and one or more trench body regions and one or more termination body regions provided within an upper portion of the epitaxial layer, the termination body regions extending into the epitaxial layer to a greater depth than the trench body regions.

Abstract: A method for producing a S-nitrosylated species is provided. The method comprises: (a) providing a deoxygenated, alkaline aqueous solution comprising a thiol and a nitrite-bearing species; (b) acidifying the solution by adding acid to the solution while concurrently mixing the solution (e.g., by vigorously stirring the solution) to produce the S-nitrosylated species; and (c) isolating the S-nitrosylated species. The nitrite-bearing species can be, for example, an inorganic nitrite, such as an alkali metal nitrite, or an organic nitrite, such as an alkyl nitrite (e.g., ethyl nitrite, amyl nitrite, isobutyl nitrite or t-butyl nitrite). The thiol is preferably a thiol-containing polysaccharide, a thiol-containing lipoprotein, a thiol-containing amino acid or a thiol-containing protein, and more preferably a thiol-containing polysaccharide such as thiolated cyclodextrin. In many preferred embodiments, the S-nitrosylated species is insoluble in the acidified solution, precipitating upon formation.

Abstract: A method of manufacturing one or more trench DMOS transistors is provided. In this method, one or more or more body regions adjacent one or more trenches are provided. The one or more trenches are lined with a first insulating layer. A portion of the first insulating layer is removed along at least the upper sidewalls of the trenches, exposing portions of the body regions. An oxide layer is then formed over at least the exposed portions of the body regions, resulting in regions of reduced majority carrier concentration within the body regions adjacent the oxide layer. This modification of the majority carrier concentration in the body regions is advantageous in that a low threshold voltage can be established within the DMOS transistor without resorting to a thinner gate oxide (which would reduce yield and switching speed) and without substantially increasing the likelihood of punch-through.