Abstract: An arrangement for a multiprocessor RISC system enables each CPU of the system to test the control logic of its cache by indirectly examining states of the caches and comparing those states to predetermined valid cache states of the system. The arrangement includes a plurality of processes configured to acquire information from selected block entries of the caches. The information is then compared with an array of predetermined valid cache states contained in a state table to detect invalid cache states. A cache examining protocol defines the operational procedures followed by the processes when acquiring and examining the information.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: A processor and method for delaying the processing of cache coherency transactions during outstanding cache fills in a multi-processor system using a shared memory. A first processor fetches data having a specified address by addressing a cache memory, and when the specified address is not in the cache, saving the specified address in a fill address memory, and sending a fill request to the shared memory. Before return of fill data, the first processor receives a cache coherency request including the specified address from a second processor requesting invalidation of an addressed block of data. The first processor responds by checking whether the fill address memory includes the specified address, and upon finding the specified address in the fill address memory, delaying execution of the cache coherency request until the fill data is returned, and when the fill data is returned, using the fill data without retaining a validated block of the fill data in the cache.

Abstract: A processor and method for preventing access to a locked memory block in a multiprocessor computer system. The processor has a cache memory and records a memory lock in a content-addressable memory separate from the cache memory. Preferably, outstanding cache fills are recorded in the same content addressable memory as memory locks, and a memory lock or an outstanding cache fill delays the execution of a cache coherency request upon the same memory block. When a cache coherency request is received from another processor, the address of the cache coherency request is compared to addresses stored in the content addressable memory, and when there is a match, a bit in the matching entry is set to indicate a delayed request that is executed after the lock is unlocked or the cache is refilled. In a specific embodiment, a memory lock or an outstanding cache fill also stalls a processor read or write to the same memory block.

Abstract: Apparatus for patching cables includes a panel 10, FIG. 2 having a patch side for exposing patching connectors, and a punch-down side opposite the patch side for exposing punch-down terminals associated with the connectors. A bracket 12, FIG. 2 supports the panel in a vertical position with the patch side exposed to users. Pivots attach one edge of the panel to the bracket so that the panel can be tilted about the pivot into a position in which the patch side is no longer exposed to users and the punch-down side is exposed to users. There is a supporting surface 40, FIG. 2 for supporting the patch side, when tilted, sufficiently to permit punching down of wires on the punch-down side. The panel may include color coded marking on the patch side for classifying the connector application.

Abstract: A computer system including a plurality of processors and a bus coupling the processors to one another via respective bus interfaces. The bus includes a plurality of slots for coupling the interfaces to the bus. Each interface includes an ID register coupled to the interface device, the ID register containing identification information unique to the slot of the bus used to couple the respective interface to the bus. The interface device is responsive to an address command cycle of the bus to place the identification information from the ID register on the bus during a READ bus transaction initiated by the interface and directed to another slot of the bus. A processor requiring identification of the corresponding slot causes the respective interface to initiate a READ bus transaction directed to another slot of the bus.

Abstract: N.sub.2 implantation is used to increase the etch rate of a sacrificial oxide (sometimes referred to as the first gate oxide) in integrated circuitry. This implantation allows etching selectivity by changing the relative etch rates of materials. In the specific implementation described, a field oxide is also provided and this implantation increases the etch rate of the sacrificial oxide relative to that of the field oxide. No heat treatment is applied to the implanted material prior to etching having the ability to repair the damage caused by the bombardment.

Abstract: Integrated circuit package (10) includes a substrate (12) comprising a porous ceramic body (14). A non-porous covering (16) provides a hermetic seal around the porous ceramic body (14). A heat transfer liquid (18) partially fills pores (30) of the porous ceramic body (14). A plurality of integrated circuit chips (20) are attached to a surface of the substrate (12) by epoxy, solder or other bonds (22). On an opposite surface, the substrate (12) includes a plurality of heat transfer fins (24). In use, the heat transfer liquid (18) in the ceramic body (14) is vaporized to fill the balance of the pores (30) and condensed in a continuous heat pipe cycle to remove heat from the integrated circuits (20) mounted on the substrate.

Abstract: For enhanced resistance to electromigration failure, a thin metal film interconnect on an integrated circuit chip should use multiple parallel minimum-width lines when the minimum linewidth is less than one and one-half times the mean grain size of the metal film. When the interconnect is longer than a certain predetermined length, then the multiple lines of the interconnect should have intermediate interconnections or bridges between neighboring ones of the multiple lines. When the interconnect is many times longer than the predetermined length, then the bridges define slots between the neighboring lines, and the slots should have a length of about the predetermined length. When the interconnect is many times longer than the predetermined length and the interconnect has more than two parallel lines, then the slots on one side of a parallel line should be staggered or offset with respect to the slots on the other side of the parallel line.

Abstract: A voltage level conversion buffer circuit including a first and a second transistor each having a gate, a drain, and a source. The drain of the first transistor and the gate of the second transistor are connected together to provide an input to the buffer circuit, and the gate of the first transistor and the drain of the second transistor are connected to a supply voltage. The sources of the first and second transistors are connected together to provide an output for the buffer circuit.

Abstract: A frame assembly for rack-mountable components. A rectangular top frame having a tubular perimeter is connected by four vertical rails to a bottom frame which also has a tubular perimeter as well as tubular members which span it. Both and top and bottom frames each provide an unobstructed central area which may be used for ventilation or application of electromagnetic shielding.

Abstract: A method of constructing opto-electronic integrated circuit packages passively aligns optical fibers inserted through holes in a package lid which are arranged in a pattern which corresponds with the pattern of emitters and receivers on a circuit die. When the lid is aligned with a package base to which the die is attached at a predetermined location, the fibers simultaneously couple to the emitters and receivers. The package components are each formed with alignment indicators. To assemble the packages, the alignment indicators are optically aligned to orient the components properly and the components are positioned such that centers of particular indicators are in predetermined positions relative to the centers other indicators. The components are then held in position while an affixation process secures them in place. Before the lid is secured to the base, a laser drills optic fiber holes to precise sizes in an array which corresponds with the locations of emitters and receivers on the die.

Abstract: A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter.

Abstract: A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a clock repeater chip, a module transmission network and a clock distribution network of an integrated circuit (IC) chip associated with a clock repeater chip. Circuits of the remote delay regulator are contained on the repeater chip and on the associated IC chip. Delay measurement of the remote IC clock distribution network is provided by sensing the clock signal at the beginning of the network using a BEFORE sense tap and at the end of the network using an AFTER sense tap. The BEFORE and AFTER sense taps are routed to a signal generation circuit on the repeater chip where measurement signals are generated that define the beginning and end of a measurement cycle.

Abstract: A distributed digital data processing system including a host and at least one node interconnected by a communications link. In response to a boot command, the node requests its boot image from the host over the communications link. The host then provides pointers to portions of the boot image to the node. The node then retrieves the portions of the boot image identified by the pointers. These operations are repeated until node retrieves the entire boot image. By having the host supply pointers to the boot image and the node perform the retrieval operations in response to the pointers, the host is freed to perform other operations while the node is actually performing the retrieval operations.

Abstract: The present invention is directed to a control flow logic device for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor. The control flow logic includes an error checker to check data received from the bus for hard errors and parity errors and an ECC generator to generate an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected by the error checker and to a good ECC in the absence of a hard error. An error signal generator is utilized to generate and transmit an error signal to the processor when there is a hard error or a parity error in the received data and a data mover transmits the received data and the ECC to the processor.

Abstract: An apparatus for memory management in network systems provides added margins of reliability for the receipt of vital maintenance operations protocol (MOP) and station management packets (SMP). In addition, additional overflow allocations of buffers are assigned for receipt of critical system packets which otherwise would typically be discarded in the event of a highly congested system. Thus, if a MOP or a SMP packet is received from the network when the allocated space for storing these types of packets in full, the packets are stored in the overflow allocations, and thus the critical packets are not lost.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: A method and device for receiving data in a synchronous communication system. Data can be accurately transferred between two subsystems in a synchronous system even where the clock skew and propagation delay between the two subsystems is unlimited. The receiving subsystem is initialized to ensure synchronous data transfer over a theoretically infinite range. The transmitting subsystem transmits data and a forwarded clock to the receiving subsystem. Data is captured in three state devices arranged in parallel to eliminate minimum delay requirements and to expand data valid time. The captured data is then aligned to the clock of the receiving subsystem by controlling a multiplexer which selects the proper state device output to pass to another state device for alignment to the receiving subsystem's clock. The multiplexer is controlled by a circuit which monitors the capturing of the incoming data and determines the correct state device output to select for proper data alignment.